Just to hammer on anything at once, and hopefully catch weird
interactions if they exist.
def test(self):
previous_hart_count = [0 for h in self.target.harts]
def test(self):
previous_hart_count = [0 for h in self.target.harts]
+ previous_interrupt_count = [0 for h in self.target.harts]
for _ in range(10):
self.gdb.c(wait=False)
for _ in range(10):
self.gdb.c(wait=False)
+ self.gdb.p("$mie")
+ self.gdb.p("$mip")
+ self.gdb.p("$mstatus")
+ self.gdb.p("$priv")
self.gdb.p("buf", fmt="")
hart_count = self.gdb.p("hart_count")
self.gdb.p("buf", fmt="")
hart_count = self.gdb.p("hart_count")
+ interrupt_count = self.gdb.p("interrupt_count")
for i, h in enumerate(self.target.harts):
assertGreater(hart_count[i], previous_hart_count[i])
for i, h in enumerate(self.target.harts):
assertGreater(hart_count[i], previous_hart_count[i])
+ assertGreater(interrupt_count[i], previous_interrupt_count[i])
self.gdb.select_hart(h)
pc = self.gdb.p("$pc")
self.gdb.stepi()
self.gdb.select_hart(h)
pc = self.gdb.p("$pc")
self.gdb.stepi()
-#define STACK_SIZE (74 * XLEN / 8)
+#define STACK_SIZE (90 * XLEN / 8)
#if XLEN == 64
# define LREG ld
#if XLEN == 64
# define LREG ld
typedef struct {
int counter;
} atomic_t;
typedef struct {
int counter;
} atomic_t;
-#define csr_read(csr) \
-({ \
- register unsigned long __v; \
- __asm__ __volatile__ ("csrr %0, " #csr \
- : "=r" (__v)); \
- __v; \
-})
-
static inline void mb(void)
{
__asm__ __volatile__ ("fence");
static inline void mb(void)
{
__asm__ __volatile__ ("fence");
static atomic_t buf_lock = { .counter = 0 };
static char buf[32];
static int buf_initialized;
static atomic_t buf_lock = { .counter = 0 };
static char buf[32];
static int buf_initialized;
-static unsigned hart_count[2];
+static unsigned hart_count[NHARTS];
+static unsigned interrupt_count[NHARTS];
-static const char case_bit = 'a' - 'A';
-volatile int initialized;
+static unsigned delta = 0x100;
+void *increment_count(unsigned hartid, unsigned mcause, void *mepc, void *sp)
+{
+ interrupt_count[hartid]++;
+ MTIMECMP[hartid] = MTIME + delta;
+ return mepc;
+}
int main()
{
uint32_t hartid = csr_read(mhartid);
hart_count[hartid] = 0;
int main()
{
uint32_t hartid = csr_read(mhartid);
hart_count[hartid] = 0;
+ interrupt_count[hartid] = 0;
+
+ set_trap_handler(increment_count);
+ // Despite being memory-mapped, there appears to be one mtimecmp
+ // register per hart. The spec does not address this.
+ MTIMECMP[hartid] = MTIME + delta;
+ enable_timer_interrupts();
while (1) {
get_lock(&buf_lock);
while (1) {
get_lock(&buf_lock);
if (!buf_initialized) {
for (unsigned i = 0; i < sizeof(buf); i++) {
if (!buf_initialized) {
for (unsigned i = 0; i < sizeof(buf); i++) {
buf[i] = 'a' + ((i + hartid + hart_count[hartid]) % 26);
}
put_lock(&buf_lock);
buf[i] = 'a' + ((i + hartid + hart_count[hartid]) % 26);
}
put_lock(&buf_lock);
def print_log(path):
header(path)
def print_log(path):
header(path)
- lines = open(path, "r").readlines()
- for l in lines:
+ for l in open(path, "r"):
sys.stdout.write(l)
print
sys.stdout.write(l)
print