Cover all combinations of 32,64 bit XLEN with F and FD extensions.
Finishes Issue https://github.com/riscv/riscv-openocd/issues/110
self.gdb.stepi()
assertLess(abs(float(self.gdb.p_raw("$%s" % name)) - b), .001)
assertLess(abs(float(self.gdb.p_raw("$%s" % alias)) - b), .001)
self.gdb.stepi()
assertLess(abs(float(self.gdb.p_raw("$%s" % name)) - b), .001)
assertLess(abs(float(self.gdb.p_raw("$%s" % alias)) - b), .001)
+
+ size = self.gdb.p("sizeof($%s)" % name)
+ if self.hart.extensionSupported('D'):
+ assertEqual(size, 8)
+ else:
+ assertEqual(size, 4)
else:
output = self.gdb.p_raw("$" + name)
assertEqual(output, "void")
else:
output = self.gdb.p_raw("$" + name)
assertEqual(output, "void")
timeout_sec = 30
def create(self):
timeout_sec = 30
def create(self):
- return testlib.Spike(self)
+ return testlib.Spike(self, isa="RV32IMAFC")
timeout_sec = 30
def create(self):
timeout_sec = 30
def create(self):
- return testlib.Spike(self)
+ # 64-bit FPRs on 32-bit target
+ return testlib.Spike(self, isa="RV32IMAFDC")
timeout_sec = 60
def create(self):
timeout_sec = 60
def create(self):
- return testlib.Spike(self)
+ return testlib.Spike(self, isa="RV64IMAFD")
timeout_sec = 30
def create(self):
timeout_sec = 30
def create(self):
- return testlib.Spike(self)
+ # 32-bit FPRs only
+ return testlib.Spike(self, isa="RV64IMAFC")
raise Exception("Compile failed!")
class Spike(object):
raise Exception("Compile failed!")
class Spike(object):
- def __init__(self, target, halted=False, timeout=None, with_jtag_gdb=True):
+ def __init__(self, target, halted=False, timeout=None, with_jtag_gdb=True,
+ isa=None):
"""Launch spike. Return tuple of its process and the port it's running
on."""
self.process = None
"""Launch spike. Return tuple of its process and the port it's running
on."""
self.process = None
if target.harts:
harts = target.harts
if target.harts:
harts = target.harts
assert len(set(t.xlen for t in harts)) == 1, \
"All spike harts must have the same XLEN"
assert len(set(t.xlen for t in harts)) == 1, \
"All spike harts must have the same XLEN"
- if harts[0].xlen == 32:
- cmd += ["--isa", "RV32G"]
+ if self.isa:
+ isa = self.isa
- cmd += ["--isa", "RV64G"]
+ isa = "RV%dG" % harts[0].xlen
+
+ cmd += ["--isa", isa]
assert len(set(t.ram for t in harts)) == 1, \
"All spike harts must have the same RAM layout"
assert len(set(t.ram for t in harts)) == 1, \
"All spike harts must have the same RAM layout"