projects
/
sifive-blocks.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
|
inline
| side by side (parent:
5b74df2
)
uart: make it easy to simulate large text printouts (#33)
author
Wesley W. Terpstra
<wesley@sifive.com>
Thu, 10 Aug 2017 23:32:48 +0000
(16:32 -0700)
committer
GitHub
<noreply@github.com>
Thu, 10 Aug 2017 23:32:48 +0000
(16:32 -0700)
src/main/scala/devices/uart/UART.scala
patch
|
blob
|
history
diff --git
a/src/main/scala/devices/uart/UART.scala
b/src/main/scala/devices/uart/UART.scala
index 58722e112eaafe5edebaf9b121b6162b2edd853b..de2cf554a33c1a4d061317b5f182619cee25fe98 100644
(file)
--- a/
src/main/scala/devices/uart/UART.scala
+++ b/
src/main/scala/devices/uart/UART.scala
@@
-69,10
+69,14
@@
class UARTTx(c: UARTParams)(implicit p: Parameters) extends UARTModule(c)(p) {
val out = Reg(init = Bits(1, 1))
io.out := out
val out = Reg(init = Bits(1, 1))
io.out := out
+ val plusarg_tx = PlusArg("uart_tx", 1, "Enable/disable the TX to speed up simulation").orR
+
val busy = (counter =/= UInt(0))
io.in.ready := io.en && !busy
when (io.in.fire()) {
val busy = (counter =/= UInt(0))
io.in.ready := io.en && !busy
when (io.in.fire()) {
- printf("%c", io.in.bits)
+ printf("UART TX (%x): %c\n", io.in.bits, io.in.bits)
+ }
+ when (io.in.fire() && plusarg_tx) {
shifter := Cat(io.in.bits, Bits(0, 1))
counter := Mux1H((0 until uartStopBits).map(i =>
(io.nstop === UInt(i)) -> UInt(n + i + 1)))
shifter := Cat(io.in.bits, Bits(0, 1))
counter := Mux1H((0 until uartStopBits).map(i =>
(io.nstop === UInt(i)) -> UInt(n + i + 1)))