non-overlapping instructions ok

diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py
index b7ebf6aae9c003956f1b6884511137b5a005cbad..05183733dcc24e7773168520ee0b5cb0747c0a6c 100644 (file)
--- a/src/experiment/score6600.py
+++ b/src/experiment/score6600.py
@@ -242,7 +242,7 @@ class Scoreboard(Elaboratable):
 
         m.d.comb += intfus.fn_issue_i.eq(fn_issue_o)
         # XXX sync, so as to stop a simulation infinite loop
-        m.d.sync += issueunit.i.busy_i.eq(cu.busy_o)
+        m.d.comb += issueunit.i.busy_i.eq(cu.busy_o)
 
         #---------
         # connect fu-fu matrix
@@ -393,25 +393,25 @@ def scoreboard_sim(dut, alusim):
 
     if True:
         instrs.append((1, 1, 2, 0))
-        #instrs.append((2, 7, 1, 1))
+        instrs.append((3, 7, 4, 1))
         #instrs.append((2, 2, 3, 1))
 
     for i, (src1, src2, dest, op) in enumerate(instrs):
 
         print ("instr %d: %d %d %d %d\n" % (i, op, src1, src2, dest))
         yield from int_instr(dut, alusim, op, src1, src2, dest)
-        yield from print_reg(dut, [1,2,3])
+        yield
         while True:
-            yield
             issue_o = yield dut.issue_o
             if issue_o:
-                yield from print_reg(dut, [1,2,3])
                 for i in range(len(dut.int_insn_i)):
                     yield dut.int_insn_i[i].eq(0)
                     yield dut.reg_enable_i.eq(0)
                 break
             print ("busy",)
             yield from print_reg(dut, [1,2,3])
+            yield
+        yield from print_reg(dut, [1,2,3])
 
     yield
     yield from print_reg(dut, [1,2,3])

diff --git a/src/scoreboard/dependence_cell.py b/src/scoreboard/dependence_cell.py
index cc49ab4e1f2da8c61456368432a11b49f5c469a6..be0359c9657ded696413bf1c00b1a2626827a98d 100644 (file)
--- a/src/scoreboard/dependence_cell.py
+++ b/src/scoreboard/dependence_cell.py
@@ -33,7 +33,7 @@ class DepCell(Elaboratable):
         m.d.comb += l.r.eq(self.go_i)
 
         # Function Unit "Forward Progress".
-        m.d.comb += self.fwd_o.eq((l.q) & self.reg_i & ~self.issue_i)
+        m.d.comb += self.fwd_o.eq((cq | l.q) & self.reg_i & ~self.issue_i)
 
         # Register Select. Activated on go read/write and *current* latch set
         m.d.comb += self.rsel_o.eq((cq | l.q) & self.go_i)