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[soclayout.git] / experiments10_verilog /
2021-06-08 Jean-Paul ChaputMerge branch 'master' of ssh://libre-riscv.org:922... tree | commitdiff
2021-06-05 Luke Kenneth Casso... add vss/vdd as pins, gets the net into the VST tree | commitdiff
2021-06-05 Luke Kenneth Casso... set power type in fake pll vdd/vss tree | commitdiff
2021-06-05 Luke Kenneth Casso... whoops, fake pll/mem need vss/vdd tree | commitdiff
2021-06-05 Luke Kenneth Casso... whoops naming pads different from nets is important tree | commitdiff
2021-06-05 Luke Kenneth Casso... sort out clock names in experiments10_verilog tree | commitdiff
2021-06-05 Luke Kenneth Casso... add coresync_clk to list of HTree tree | commitdiff
2021-06-05 Luke Kenneth Casso... add dummy pll to experiments10_verilog tree | commitdiff
2021-06-05 Luke Kenneth Casso... set various clocks to use H-Tree tree | commitdiff
2021-06-05 Luke Kenneth Casso... add dummy (fake) PLL to experiments10_verilog for testing tree | commitdiff
2021-04-24 Luke Kenneth Casso... cleanup mksyms.sh to include FreePDK_C4M45 tree | commitdiff
2021-04-24 Luke Kenneth Casso... correct relative link to FreePDK45_c4m45, use submodule tree | commitdiff
2021-04-24 Jean-Paul ChaputMerge branch 'master' of ssh://libre-riscv.org:922... tree | commitdiff
2021-04-24 Jean-Paul ChaputCorrect settings for experiment10_verilog & FreePDK45. tree | commitdiff
2021-04-19 Staf Verhaegenexperiments10_verilog/freepdk_c4m45: Add link for add.py. tree | commitdiff
2021-04-19 Luke Kenneth Casso... add SPBlock512 instance generator tree | commitdiff
2021-04-19 Luke Kenneth Casso... code-comments tree | commitdiff
2021-04-19 Luke Kenneth Casso... add two SRAMs, document how to do more tree | commitdiff
2021-04-14 Luke Kenneth Casso... add an SRAM and wishbone to add test (makes it bigger) tree | commitdiff
2021-04-14 Luke Kenneth Casso... connect up boundary scan to inputs/outputs tree | commitdiff
2021-04-13 Luke Kenneth Casso... use METAL10 for topRoutingLayer tree | commitdiff
2021-04-13 Luke Kenneth Casso... whoops forgot settings.py tree | commitdiff
2021-04-12 Luke Kenneth Casso... set routingGauge manually tree | commitdiff
2021-04-12 Luke Kenneth Casso... enable HFNS in adder tree | commitdiff
2021-04-12 Luke Kenneth Casso... include (but do not use) FreePDK45 in experiments10 tree | commitdiff
2021-04-12 Luke Kenneth Casso... different FreePDK45 experiments10 chip size tree | commitdiff
2021-04-12 Luke Kenneth Casso... experimentation to get experiment10_verilog work with... tree | commitdiff
2021-04-12 Luke Kenneth Casso... add FreePDK45 experiments10_verilog doDesign.py tree | commitdiff
2021-04-12 Luke Kenneth Casso... add FreePDK45 variant of experiments10_verilog tree | commitdiff
2021-04-12 Luke Kenneth Casso... rename sys_clk in adder test experiments10_verilog... tree | commitdiff
2021-04-12 Luke Kenneth Casso... rename JTAG port in adder test experiments10_verilog... tree | commitdiff
2021-04-12 Luke Kenneth Casso... back to "working" verilog add tree | commitdiff
2021-04-09 Luke Kenneth Casso... sigh, broken experiment10_verilog tree | commitdiff
2021-04-09 Luke Kenneth Casso... whitespace cleanup tree | commitdiff
2021-04-09 Luke Kenneth Casso... pad name starts with p_ tree | commitdiff
2021-04-09 Luke Kenneth Casso... rename design of experiments10 to match ls180 chip... tree | commitdiff
2021-04-02 Luke Kenneth Casso... experiment with nmigen verilog generation tree | commitdiff