Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn

   1 # Comparative analysis with Andes Packed ISA proposal
   2
   3 ## Register file
   4
   5 The default Harmonised RVP GPR register file is divided into a lower bank of Vector[INT8] and an upper bank of Vector[INT16].
   6 In contrast, the Andes Packed SIMD ISA permits any GPR to be used for either INT8 or INT16 vector operations
   7
   8 | Register           | Andes ISA                              | Harmonised RVP ISA            |
   9 | ------------------ | -------------------------              | -------------------           |
  10 | v0                 | Hardwired zero                         | Hardwired zero                |
  11 | v1                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | Predicate mask                |
  12 | |  |  |
  13 | v2                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xSINT8]  |
  14 | v3                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xSINT8]  |
  15 | v4                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xSINT8]  |
  16 | v5                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xSINT8]  |
  17 | v6                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xSINT8]  |
  18 | v7                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xSINT8]  |
  19 | v8                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8]  |
  20 | v9                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8]  |
  21 | v10                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8]  |
  22 | v11                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8]  |
  23 | v12                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8]  |
  24 | v13                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8]  |
  25 | v14                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8]  |
  26 | v15                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8]  |
  27 | |  |  |
  28 | v16                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] |
  29 | v17                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] |
  30 | v18                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] |
  31 | v19                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] |
  32 | v20                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] |
  33 | v21                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] |
  34 | v22                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] |
  35 | v23                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] |
  36 | v24                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xUINT16] |
  37 | v25                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xUINT16] |
  38 | v26                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xUINT16] |
  39 | v27                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xUINT16] |
  40 | v28                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xUINT16] |
  41 | v29                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xUINT16] |
  42 | |  |  |
  43 | v30                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[1xSINT32] |
  44 | v31                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[1xSINT32] |
  45
  46
  47 ## 16-bit Arithmetic
  48
  49 | Andes Mnemonic           | 16-bit Instruction        | Harmonised RVP Equivalent |
  50 | ------------------ | ------------------------- | ------------------- |
  51 | ADD16 rt, ra, rb   | Add                       | VADD (v16 <= rt,ra,rb <= v29), mm=00|
  52 | RADD16 rt, ra, rb  | Signed Halving add        | RADD (v16 <= rt,ra,rb <= v23), mm=00|
  53 | URADD16 rt, ra, rb | Unsigned Halving add      | RADD (v24 <= rt,ra,rb <= v29), mm=00|
  54 | KADD16 rt, ra, rb  | Signed Saturating add     | VADD (v16 <= rt,ra,rb <= v23), mm=01|
  55 | UKADD16 rt, ra, rb | Unsigned Saturating add   | VADD (v24 <= rt,ra,rb <= v29), mm=01|
  56 | SUB16 rt, ra, rb   | Subtract                  | VSUB (v16 <= rt,ra,rb <= v29), mm=00|
  57 | RSUB16 rt, ra, rb  | Signed Halving sub        | RSUB (v16 <= rt,ra,rb <= v23), mm=00|
  58 | URSUB16 rt, ra, rb | Unsigned Halving sub                | RSUB (v24 <= rt,ra,rb <= v29), mm=00|
  59 | KSUB16 rt, ra, rb  | Signed Saturating sub               | VSUB (v16 <= rt,ra,rb <= v23), mm=01|
  60 | UKSUB16 rt, ra, rb | Unsigned Saturating sub             | VSUB (v24 <= rt,ra,rb <= v29), mm=01|
  61 | CRAS16 rt, ra, rb  | Cross Add & Sub                     | |
  62 | RCRAS16 rt, ra, rb | Signed Halving Cross Add & Sub      | |
  63 | URCRAS16 rt, ra, rb| Unsigned Halving Cross Add & Sub    | |
  64 | KCRAS16 rt, ra, rb | Signed Saturating Cross Add & Sub   | |
  65 | UKCRAS16 rt, ra, rb| Unsigned Saturating Cross Add & Sub | |
  66 | CRSA16 rt, ra, rb  | Cross Sub & Add                     | |
  67 | RCRSA16 rt, ra, rb | Signed Halving Cross Sub & Add      | |
  68 | URCRSA16 rt, ra, rb| Unsigned Halving Cross Sub & Add    | |
  69 | KCRSA16 rt, ra, rb | Signed Saturating Cross Sub & Add   | |
  70 | UKCRSA16 rt, ra, rb| Unsigned Saturating Cross Sub & Add | |
  71
  72 ## 8-bit Arithmetic
  73
  74 | Andes Mnemonic           | 8-bit Instruction        | Harmonised RVP Equivalent |
  75 | ------------------ | ------------------------- | ------------------- |
  76 | ADD8 rt, ra, rb    | Add                       | VADD (v2 <= rt,ra,rb <= v15), mm=00 |
  77 | RADD8 rt, ra, rb   | Signed Halving add        | RADD (v2 <= rt,ra,rb <= v7), mm=00 |
  78 | URADD8 rt, ra, rb  | Unsigned Halving add      | RADD (v8 <= rt,ra,rb <= v15), mm=00 |
  79 | KADD8 rt, ra, rb   | Signed Saturating add     | VADD (v2 <= rt,ra,rb <= v7), mm=01 |
  80 | UKADD8 rt, ra, rb  | Unsigned Saturating add   | VADD (v8 <= rt,ra,rb <= v15), mm=01 |
  81 | SUB8 rt, ra, rb    | Subtract                  | VSUB (v2 <= rt,ra,rb <= v15), mm=00 |
  82 | RSUB8 rt, ra, rb   | Signed Halving sub        | RSUB (v2 <= rt,ra,rb <= v7), mm=00 |
  83 | URSUB8 rt, ra, rb  | Unsigned Halving sub      | RSUB (v8 <= rt,ra,rb <= v15), mm=00 |
  84 | KSUB8 rt, ra, rb   | Signed Saturating sub        | VSUB (v2 <= rt,ra,rb <= v7), mm=01 |
  85 | UKSUB8 rt, ra, rb  | Unsigned Saturating sub      | VSUB (v8 <= rt,ra,rb <= v15), mm=01 |
  86
  87 ## 16-bit Shifts
  88
  89 SRA[I]16/SRL[I]16/SLL[I]16 to be mapped to VOP shift instructions in same manner as ADD16/SUB16
  90
  91 The “K” (Saturation) and “u” (Rounding) variants could be encoded using VOP’s mm field (mm=01 is saturated or rounded shift, mm=00 is standard VOP shift)
  92
  93 | Andes Mnemonic             | 16-bit Instruction         | Harmonised RVP Equivalent |
  94 | ------------------   | -------------------------  | ------------------- |
  95 | SRA16 rt, ra, rb     | Shift right arithmetic     | VSRA (v16 <= rt,ra,rb <= v29), mm=00|
  96 | SRAI16 rt, ra, im    | Shift right arithmetic imm | VSRAI (v16 <= rt,ra <= v29), mm=00|
  97 | SRA16.u rt, ra, rb   | Rounding Shift right arithmetic     | VSRA (v16 <= rt,ra,rb <= v29), mm=01|
  98 | SRAI16.u rt, ra, im  | Rounding Shift right arithmetic imm | VSRAI (v16 <= rt,ra <= v29), mm=01|
  99 | SRL16 rt, ra, rb     | Shift right logical        | VSRL (v16 <= rt,ra,rb <= v29), mm=00|
 100 | SRLI16 rt, ra, im    | Shift right logical imm    | VSRLI (v16 <= rt,ra <= v29), mm=00|
 101 | SRL16.u rt, ra, rb   | Rounding Shift right logical     | VSRL (v16 <= rt,ra,rb <= v29), mm=01|
 102 | SRLI16.u rt, ra, im  | Rounding Shift right logical imm | VSLRI (v16 <= rt,ra <= v29), mm=01|
 103 | SLL16 rt, ra, rb     | Shift left logical         | VSLL (v16 <= rt,ra,rb <= v29), mm=00|
 104 | SLLI16 rt, ra, im    | Shift left logical imm     | VSLLI (v16 <= rt,ra <= v29), mm=00|
 105 | KSLL16 rt, ra, rb    | Saturating Shift left logical       | VSLL (v16 <= rt,ra,rb <= v29), mm=01|
 106 | KSLLI16 rt, ra, im   | Saturating Shift left logical imm   | VSLLI (v16 <= rt,ra <= v29), mm=01|
 107 | KSLRA16 rt, ra, rb    | Saturating Shift left logical or Shift right arithmetic              ||
 108 | KSLRA16.u rt, ra, rb  | Saturating Shift left logical or Rounding Shift right arithmetic     ||
 109
 110
 111 ## 8-bit Shifts
 112
 113 Andes SIMD Packed ISA omits 8 bit shifts, but these can be encoded in Harmonised RVP as follows:
 114
 115 | Andes Mnemonic             | 8-bit Instruction         | Harmonised RVP Equivalent |
 116 | ------------------   | -------------------------  | ------------------- |
 117 | n/a     | Shift right arithmetic     | VSRA (v2 <= rt,ra,rb <= v15), mm=00|
 118 | n/a     | Shift right arithmetic imm | VSRAI (v2 <= rt,ra <= v15), mm=00|
 119 | n/a     | Rounding Shift right arithmetic     | VSRA (v2 <= rt,ra,rb <= v15), mm=01|
 120 | n/a     | Rounding Shift right arithmetic imm | VSRAI (v2 <= rt,ra <= v15), mm=01|
 121 | n/a     | Shift right logical        | VSRL (v2 <= rt,ra,rb <= v15), mm=00|
 122 | n/a     | Shift right logical imm    | VSRLI (v2 <= rt,ra <= v15), mm=00|
 123 | n/a     | Rounding Shift right logical     | VSRL (v2 <= rt,ra,rb <= v15), mm=01|
 124 | n/a     | Rounding Shift right logical imm | VSLRI (v2 <= rt,ra <= v15), mm=01|
 125 | n/a     | Shift left logical         | VSLL (v2 <= rt,ra,rb <= v15), mm=00|
 126 | n/a     | Shift left logical imm     | VSLLI (v2 <= rt,ra <= v15), mm=00|
 127 | n/a     | Saturating Shift left logical       | VSLL (v2 <= rt,ra,rb <= v15), mm=01|
 128 | n/a     | Saturating Shift left logical imm   | VSLLI (v2 <= rt,ra <= v15), mm=01|
 129
 130 ## 16-bit Comparison instructions
 131
 132 | Andes Mnemonic           | 16-bit Instruction        | Harmonised RVP Equivalent |
 133 | ------------------   | ------------------------- | ------------------- |
 134 | CMPEQ16 rt, ra, rb   | Compare equal             | VSEQ (v16 <= rt,ra,rb <= v29), mm=00|
 135 | SCMPLT16 rt, ra, rb   | Signed Compare less than        | !VSGT (v16 <= rt,ra,rb <= v23), mm=00|
 136 | SCMPLE16 rt, ra, rb   | Signed Compare less or equal    | VSLE (v16 <= rt,ra,rb <= v23), mm=00|
 137 | UCMPLT16 rt, ra, rb   | Unsigned Compare less than      | !VSGT (v24 <= rt,ra,rb <= v29), mm=00|
 138 | UCMPLE16 rt, ra, rb   | Unsigned Compare less or equal  | VSLE (v24 <= rt,ra,rb <= v29), mm=00|
 139
 140 ## 8-bit Comparison instructions
 141
 142 | Andes Mnemonic           | 8-bit Instruction        | Harmonised RVP Equivalent |
 143 | ------------------   | ------------------------- | ------------------- |
 144 | CMPEQ8 rt, ra, rb   | Compare equal             | VSEQ (v2 <= rt,ra,rb <= v7), mm=00|
 145 | SCMPLT8 rt, ra, rb   | Signed Compare less than        | !VSGT (v2 <= rt,ra,rb <= v7), mm=00|
 146 | SCMPLE8 rt, ra, rb   | Signed Compare less or equal    | VSLE (v2 <= rt,ra,rb <= v7), mm=00|
 147 | UCMPLT8 rt, ra, rb   | Unsigned Compare less than      | !VSGT (v8 <= rt,ra,rb <= v15), mm=00|
 148 | UCMPLE8 rt, ra, rb   | Unsigned Compare less or equal  | VSLE (v8 <= rt,ra,rb <= v15), mm=00|
 149
 150 ## 16-bit Miscellaneous instructions
 151
 152 | Andes Mnemonic      | 16-bit Instruction                | Harmonised RVP Equivalent |
 153 | ------------------  | ------------------------          | ------------------- |
 154 | SMIN16 rt, ra, rb   | Signed minimum                    | VMIN (v16 <= rt,ra,rb <= v23), mm=00|
 155 | UMIN16 rt, ra, rb   | Unsigned minimum                  | VMIN (v24 <= rt,ra,rb <= v29), mm=00|
 156 | SMAX16 rt, ra, rb   | Signed maximum                    | VMAX (v16 <= rt,ra,rb <= v23), mm=00|
 157 | UMAX16 rt, ra, rb   | Unsigned maximum                  | VMAX (v24 <= rt,ra,rb <= v29), mm=00|
 158 | SCLIP16 rt, ra, im  | Signed clip                       | ?VCLIP (v16 <= rt,ra,rb <= v23), mm=01|
 159 | UCLIP16 rt, ra, im  | Unsigned clip                     | ?VCLIP (v24 <= rt,ra,rb <= v29), mm=01|
 160 | KMUL16 rt, ra, rb   | Signed multiply 16x16->16         | VMUL (v16 <= rt,ra,rb <= v23), mm=01|
 161 | KMULX16 rt, ra, rb  | Signed crossed multiply 16x16->16 | |
 162 | SMUL16 rt, ra, rb   | Signed multiply 16x16->32         | VMUL (30 <= rt <= 31, v16 <= ra,rb <= v23), mm=00|
 163 | SMULX16 rt, ra, rb  | Signed crossed multiply 16x16->32 | |
 164 | UMUL16 rt, ra, rb   | Signed multiply 16x16->32         | VMUL (30 <= rt <= 31, v24 <= ra,rb <= r31), mm=00|
 165 | UMULX16 rt, ra, rb  | Signed crossed multiply 16x16->32 | |
 166 | KABS16 rt, ra       | Saturated absolute value          | VSGNX (v16 <= rt <= v29, v16 <= ra,rb <= v23, mm=01) |
 167
 168 ## 8-bit Miscellaneous instructions
 169
 170 | Andes Mnemonic           | 8-bit Instruction        | Harmonised RVP Equivalent |
 171 | ------------------   | ------------------------- | ------------------- |
 172 | SMIN8 rt, ra, rb   | Signed minimum           | VMIN (v2 <= rt,ra,rb <= v7), mm=00|
 173 | UMIN8 rt, ra, rb   | Unsigned minimum         | VMIN (v8 <= rt,ra,rb <= v15), mm=00|
 174 | SMAX8 rt, ra, rb   | Signed maximum           | VMAX (v2 <= rt,ra,rb <= v7), mm=00|
 175 | UMAX8 rt, ra, rb   | Unsigned maximum         | VMAX (v8 <= rt,ra,rb <= v15), mm=00|
 176 | KABS8 rt, ra       | Saturated absolute value | VSGNX (v2 <= rt <= v15, v2 <= ra,rb <= v8, mm=01) |
 177
 178 ## 8-bit Unpacking instructions
 179
 180 | Andes Mnemonic           | 8-bit Instruction       | Harmonised RVP Equivalent |
 181 | ------------------   | -------------------------   | ------------------- |
 182 | SUNPKD810 rt, ra     | Signed unpack bytes 1 & 0   | VMV (v16<= rt <= 23, v2 <= ra <= v7), mm=00|
 183 | SUNPKD820 rt, ra     | Signed unpack bytes 2 & 0   | |
 184 | SUNPKD830 rt, ra     | Signed unpack bytes 3 & 0   | |
 185 | SUNPKD831 rt, ra     | Signed unpack bytes 3 & 1   | |
 186 | ZUNPKD810 rt, ra     | Unsigned unpack bytes 1 & 0 | VMV (v24<= rt <= 31, v8 <= ra <= v15), mm=00|
 187 | ZUNPKD820 rt, ra     | Unsigned unpack bytes 2 & 0 | |
 188 | ZUNPKD830 rt, ra     | Unsigned unpack bytes 3 & 0 | |
 189 | ZUNPKD831 rt, ra     | Unsigned unpack bytes 3 & 1 | |