fosdem2024_formal: add slides and diagrams
[libreriscv.git] / conferences / ep2021.mdwn
1 # Schedule
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3 * <https://ep2021.europython.eu/faq/#nodes>
4 * <https://ep2021.europython.eu/schedule/>
5 * free live stream access <https://ep2021.europython.eu/registration/buy-tickets/>
6 * <https://ep2021.europython.eu/talks/46wiGSm-the-libre-soc-project/>
7 * <https://ep2021.europython.eu/schedule/30-july?selected=46wiGSm-the-libre-soc-project#12:15-UTC>
8 * <https://youtu.be/wH3RBfzuPlI?t=4791> Brian Room, start of talk
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10 # Proposal
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12 **The Libre-SOC Project**
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14 *designing a quad core hybrid 3D CPU-GPU-VPU entirely in python*
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16 The Libre-SOC Project aims to bring to market a mass-volume System-on-a-Chip suitable for use in smartphones netbooks tablets and chromebooks, which is end-user programmable right to the bedrock. No spying backdoors, no treacherous DRM. Libre to the core (literally).
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18 The Libre-SOC Project aims to bring to market a mass-volume System-on-a-Chip suitable for use in smartphones netbooks tablets and chromebooks, which is end-user programmable right to the bedrock. No spying backdoors, no treacherous DRM.
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20 Python and standard Libre Project Management is used throughout:
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22 * nmigen, a python-based HDL, is a fundamental and critical strategic choice in creating the hardware.
23 * An IEEE754 FP hardware library has been developed using nmigen/python, as are hundreds of thousands of unit tests
24 * An OpenPOWER ISA simulator is written in python, and is actually a PLY compiler based on the GardenSnake example
25 * Several thousand unit tests for the HDL and simulator are written in python
26 * coriolis2, the VLSI ASIC layout toolchain, is a mixed c++ python application
27 * Even the Standard Cell Library being used, called FlexLib, by Chips4Makers, is in python.
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29 To say that python is critical to the project would be a massive understatement. This talk will give a brief overview of the above areas and give a glimpse into why python was chosen for each.