3 * Copyright 2018 Jacob Lifshay
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in all
13 * copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 from migen
.fhdl
import verilog
32 from migen
.fhdl
.structure
import _Operator
34 from riscvdefs
import *
37 class MemoryInterface
:
38 fetch_address
= Signal(32, name
="memory_interface_fetch_address") # XXX [2:]
39 fetch_data
= Signal(32, name
="memory_interface_fetch_data")
40 fetch_valid
= Signal(name
="memory_interface_fetch_valid")
41 rw_address
= Signal(32, name
="memory_interface_rw_address") # XXX [2:]
42 rw_byte_mask
= Signal(4, name
="memory_interface_rw_byte_mask")
43 rw_read_not_write
= Signal(name
="memory_interface_rw_read_not_write")
44 rw_active
= Signal(name
="memory_interface_rw_active")
45 rw_data_in
= Signal(32, name
="memory_interface_rw_data_in")
46 rw_data_out
= Signal(32, name
="memory_interface_rw_data_out")
47 rw_address_valid
= Signal(name
="memory_interface_rw_address_valid")
48 rw_wait
= Signal(name
="memory_interface_rw_wait")
52 funct7
= Signal(7, name
="decoder_funct7")
53 funct3
= Signal(3, name
="decoder_funct3")
54 rd
= Signal(5, name
="decoder_rd")
55 rs1
= Signal(5, name
="decoder_rs1")
56 rs2
= Signal(5, name
="decoder_rs2")
57 immediate
= Signal(32, name
="decoder_immediate")
58 opcode
= Signal(7, name
="decoder_opcode")
59 act
= Signal(decode_action
, name
="decoder_action")
63 def __init__(self
, comb
, sync
):
66 self
.mpie
= Signal(name
="mstatus_mpie")
67 self
.mie
= Signal(name
="mstatus_mie")
68 self
.mstatus
= Signal(32, name
="mstatus")
70 self
.sync
+= self
.mie
.eq(0)
71 self
.sync
+= self
.mpie
.eq(0)
72 self
.sync
+= self
.mstatus
.eq(0)
76 def __init__(self
, comb
, sync
):
79 self
.meie
= Signal(name
="mie_meie")
80 self
.mtie
= Signal(name
="mie_mtie")
81 self
.msie
= Signal(name
="mie_msie")
91 def __init__(self
, comb
, sync
):
94 self
.mcause
= Signal(32)
95 self
.mepc
= Signal(32)
96 self
.mscratch
= Signal(32)
97 self
.sync
+= self
.mcause
.eq(0)
98 self
.sync
+= self
.mepc
.eq(0) # 32'hXXXXXXXX;
99 self
.sync
+= self
.mscratch
.eq(0) # 32'hXXXXXXXX;
103 def __init__(self
, comb
, sync
):
106 self
.misa
= Signal(32)
108 for l
in list(string
.ascii_lowercase
):
109 value
= 1 if l
== 'i' else 0
110 cl
.append(Constant(value
))
111 cl
.append(Constant(0, 4))
112 cl
.append(Constant(0b01, 2))
113 self
.comb
+= self
.misa
.eq(Cat(cl
))
117 def __init__(self
, comb
, sync
):
120 self
.action
= Signal(fetch_action
, name
="fetch_action")
121 self
.target_pc
= Signal(32, name
="fetch_target_pc")
122 self
.output_pc
= Signal(32, name
="fetch_output_pc")
123 self
.output_instruction
= Signal(32, name
="fetch_ouutput_instruction")
124 self
.output_state
= Signal(fetch_output_state
,name
="fetch_output_state")
127 def __init__(self
, comb
, sync
, dc
, register_rs1
):
130 self
.number
= Signal(12, name
="csr_number")
131 self
.input_value
= Signal(32, name
="csr_input_value")
132 self
.reads
= Signal(name
="csr_reads")
133 self
.writes
= Signal(name
="csr_writes")
134 self
.op_is_valid
= Signal(name
="csr_op_is_valid")
136 self
.comb
+= self
.number
.eq(dc
.immediate
)
137 self
.comb
+= self
.input_value
.eq(Mux(dc
.funct3
[2],
140 self
.comb
+= self
.reads
.eq(dc
.funct3
[1] |
(dc
.rd
!= 0))
141 self
.comb
+= self
.writes
.eq(~dc
.funct3
[1] |
(dc
.rs1
!= 0))
143 self
.comb
+= self
.get_csr_op_is_valid()
145 def get_csr_op_is_valid(self
):
146 """ determines if a CSR is valid
150 for f
in [csr_ustatus
, csr_fflags
, csr_frm
, csr_fcsr
,
151 csr_uie
, csr_utvec
, csr_uscratch
, csr_uepc
,
152 csr_ucause
, csr_utval
, csr_uip
, csr_sstatus
,
153 csr_sedeleg
, csr_sideleg
, csr_sie
, csr_stvec
,
154 csr_scounteren
, csr_sscratch
, csr_sepc
, csr_scause
,
155 csr_stval
, csr_sip
, csr_satp
, csr_medeleg
,
156 csr_mideleg
, csr_dcsr
, csr_dpc
, csr_dscratch
]:
157 c
[f
] = self
.op_is_valid
.eq(0)
159 # not-writeable -> ok
160 for f
in [csr_cycle
, csr_time
, csr_instret
, csr_cycleh
,
161 csr_timeh
, csr_instreth
, csr_mvendorid
, csr_marchid
,
162 csr_mimpid
, csr_mhartid
]:
163 c
[f
] = self
.op_is_valid
.eq(~self
.writes
)
166 for f
in [csr_misa
, csr_mstatus
, csr_mie
, csr_mtvec
,
167 csr_mscratch
, csr_mepc
, csr_mcause
, csr_mip
]:
168 c
[f
] = self
.op_is_valid
.eq(1)
170 # not implemented / default
171 for f
in [csr_mcounteren
, csr_mtval
, csr_mcycle
, csr_minstret
,
172 csr_mcycleh
, csr_minstreth
, "default"]:
173 c
[f
] = self
.op_is_valid
.eq(0)
175 return Case(self
.number
, c
)
177 def evaluate_csr_funct3_op(self
, funct3
, previous
, written
):
178 c
= { "default": written
.eq(Constant(0, 32))}
179 for f
in [F3
.csrrw
, F3
.csrrwi
]:
180 c
[f
] = written
.eq(self
.input_value
)
181 for f
in [F3
.csrrs
, F3
.csrrsi
]:
182 c
[f
] = written
.eq(self
.input_value | previous
)
183 for f
in [F3
.csrrc
, F3
.csrrci
]:
184 c
[f
] = written
.eq(~self
.input_value
& previous
)
185 return Case(funct3
, c
)
189 def __init__(self
, comb
):
192 self
.cycle_counter
= Signal(64); # TODO: implement cycle_counter
193 self
.time_counter
= Signal(64); # TODO: implement time_counter
194 self
.instret_counter
= Signal(64); # TODO: implement instret_counter
196 self
.mvendorid
= Signal(32)
197 self
.marchid
= Signal(32)
198 self
.mimpid
= Signal(32)
199 self
.mhartid
= Signal(32)
200 self
.comb
+= self
.mvendorid
.eq(Constant(0, 32))
201 self
.comb
+= self
.marchid
.eq(Constant(0, 32))
202 self
.comb
+= self
.mimpid
.eq(Constant(0, 32))
203 self
.comb
+= self
.mhartid
.eq(Constant(0, 32))
206 def __init__(self
, comb
, sync
):
210 self
.ra_en
= Signal(reset
=1, name
="regfile_ra_en") # TODO: ondemand en
211 self
.rs1
= Signal(32, name
="regfile_rs1")
212 self
.rs_a
= Signal(5, name
="regfile_rs_a")
214 self
.rb_en
= Signal(reset
=1, name
="regfile_rb_en") # TODO: ondemand en
215 self
.rs2
= Signal(32, name
="regfile_rs2")
216 self
.rs_b
= Signal(5, name
="regfile_rs_b")
218 self
.w_en
= Signal(name
="regfile_w_en")
219 self
.wval
= Signal(32, name
="regfile_wval")
220 self
.rd
= Signal(32, name
="regfile_rd")
226 def get_lsbm(self
, dc
):
227 return Cat(Constant(1),
228 Mux((dc
.funct3
[1] | dc
.funct3
[0]),
229 Constant(1), Constant(0)),
231 Constant(0b11, 2), Constant(0, 2)))
233 # XXX this happens to get done by various self.sync actions
234 #def reset_to_initial(self, m, mstatus, mie, registers):
235 # return [m.mcause.eq(0),
238 def main_block(self
, mtvec
, mip
, minfo
, misa
, csr
, mi
, m
, mstatus
, mie
,
240 load_store_misaligned
,
241 loaded_value
, alu_result
,
245 c
[FOS
.trap
] = self
.handle_trap
.eq(1)
246 c
[FOS
.valid
] = self
.handle_valid(mtvec
, mip
, minfo
, misa
, csr
, mi
, m
,
247 mstatus
, mie
, ft
, dc
,
248 load_store_misaligned
,
252 return [self
.handle_trap
.eq(0),
253 self
.regs
.w_en
.eq(0),
254 Case(ft
.output_state
, c
),
255 self
.handle_trap
.eq(0),
256 self
.regs
.w_en
.eq(0)]
258 def write_register(self
, rd
, val
):
259 return [self
.regs
.rd
.eq(rd
),
260 self
.regs
.wval
.eq(val
),
264 def handle_valid(self
, mtvec
, mip
, minfo
, misa
, csr
, mi
, m
, mstatus
, mie
,
266 load_store_misaligned
,
267 loaded_value
, alu_result
,
269 # fetch action ack trap
270 i
= If((ft
.action
== FA
.ack_trap
) |
(ft
.action
== FA
.noerror_trap
),
271 [self
.handle_trap
.eq(1),
272 self
.regs
.w_en
.eq(0) # no writing to registers
277 i
= i
.Elif((dc
.act
& DA
.load
) != 0,
279 self
.write_register(dc
.rd
, loaded_value
)
284 i
= i
.Elif((dc
.act
& DA
.op_op_imm
) != 0,
285 self
.write_register(dc
.rd
, alu_result
)
289 i
= i
.Elif((dc
.act
& DA
.lui_auipc
) != 0,
290 self
.write_register(dc
.rd
, lui_auipc_result
)
294 i
= i
.Elif((dc
.act
& (DA
.jal | DA
.jalr
)) != 0,
295 self
.write_register(dc
.rd
, ft
.output_pc
+ 4)
298 i
= i
.Elif((dc
.act
& DA
.csr
) != 0,
299 self
.handle_csr(mtvec
, mip
, minfo
, misa
, mstatus
, mie
, m
,
303 # fence, store, branch
304 i
= i
.Elif((dc
.act
& (DA
.fence | DA
.fence_i |
305 DA
.store | DA
.branch
)) != 0,
307 self
.regs
.w_en
.eq(0) # no writing to registers
312 def handle_csr(self
, mtvec
, mip
, minfo
, misa
, mstatus
, mie
, m
, dc
, csr
):
313 csr_output_value
= Signal(32)
314 csr_written_value
= Signal(32)
318 c
[csr_cycle
] = csr_output_value
.eq(minfo
.cycle_counter
[0:32])
319 c
[csr_cycleh
] = csr_output_value
.eq(minfo
.cycle_counter
[32:64])
321 c
[csr_time
] = csr_output_value
.eq(minfo
.time_counter
[0:32])
322 c
[csr_timeh
] = csr_output_value
.eq(minfo
.time_counter
[32:64])
324 c
[csr_instret
] = csr_output_value
.eq(minfo
.instret_counter
[0:32])
325 c
[csr_instreth
] = csr_output_value
.eq(minfo
.instret_counter
[32:64])
326 # mvendorid/march/mimpl/mhart
327 c
[csr_mvendorid
] = csr_output_value
.eq(minfo
.mvendorid
)
328 c
[csr_marchid
] = csr_output_value
.eq(minfo
.marchid
)
329 c
[csr_mimpid
] = csr_output_value
.eq(minfo
.mimpid
)
330 c
[csr_mhartid
] = csr_output_value
.eq(minfo
.mhartid
)
332 c
[csr_misa
] = csr_output_value
.eq(misa
.misa
)
335 csr_output_value
.eq(mstatus
.mstatus
),
336 csr
.evaluate_csr_funct3_op(dc
.funct3
, csr_output_value
,
338 mstatus
.mpie
.eq(csr_written_value
[7]),
339 mstatus
.mie
.eq(csr_written_value
[3])
343 csr_output_value
.eq(mie
.mie
),
344 csr
.evaluate_csr_funct3_op(dc
.funct3
, csr_output_value
,
346 mie
.meie
.eq(csr_written_value
[11]),
347 mie
.mtie
.eq(csr_written_value
[7]),
348 mie
.msie
.eq(csr_written_value
[3]),
351 c
[csr_mtvec
] = csr_output_value
.eq(mtvec
)
354 csr_output_value
.eq(m
.mscratch
),
355 csr
.evaluate_csr_funct3_op(dc
.funct3
, csr_output_value
,
358 m
.mscratch
.eq(csr_written_value
),
363 csr_output_value
.eq(m
.mepc
),
364 csr
.evaluate_csr_funct3_op(dc
.funct3
, csr_output_value
,
367 m
.mepc
.eq(csr_written_value
),
373 csr_output_value
.eq(m
.mcause
),
374 csr
.evaluate_csr_funct3_op(dc
.funct3
, csr_output_value
,
377 m
.mcause
.eq(csr_written_value
),
383 csr_output_value
.eq(mip
.mip
),
384 csr
.evaluate_csr_funct3_op(dc
.funct3
, csr_output_value
,
388 return [Case(csr
.number
, c
),
390 self
.write_register(dc
.rd
, csr_output_value
)
394 Module
.__init
__(self
)
395 self
.clk
= ClockSignal()
396 self
.reset
= ResetSignal()
397 self
.tty_write
= Signal()
398 self
.tty_write_data
= Signal(8)
399 self
.tty_write_busy
= Signal()
400 self
.switch_2
= Signal()
401 self
.switch_3
= Signal()
402 self
.led_1
= Signal()
403 self
.led_3
= Signal()
405 ram_size
= Constant(0x8000)
406 ram_start
= Constant(0x10000, 32)
407 reset_vector
= Signal(32)
410 reset_vector
.eq(ram_start
)
411 mtvec
.eq(ram_start
+ 0x40)
413 self
.regs
= Regs(self
.comb
, self
.sync
)
415 rf
= Instance("RegFile", name
="regfile",
416 i_ra_en
= self
.regs
.ra_en
,
417 i_rb_en
= self
.regs
.rb_en
,
418 i_w_en
= self
.regs
.w_en
,
419 o_read_a
= self
.regs
.rs1
,
420 o_read_b
= self
.regs
.rs2
,
421 i_writeval
= self
.regs
.wval
,
422 i_rs_a
= self
.regs
.rs_a
,
423 i_rs_b
= self
.regs
.rs_b
,
428 mi
= MemoryInterface()
430 mii
= Instance("cpu_memory_interface", name
="memory_instance",
431 p_ram_size
= ram_size
,
432 p_ram_start
= ram_start
,
435 i_fetch_address
= mi
.fetch_address
,
436 o_fetch_data
= mi
.fetch_data
,
437 o_fetch_valid
= mi
.fetch_valid
,
438 i_rw_address
= mi
.rw_address
,
439 i_rw_byte_mask
= mi
.rw_byte_mask
,
440 i_rw_read_not_write
= mi
.rw_read_not_write
,
441 i_rw_active
= mi
.rw_active
,
442 i_rw_data_in
= mi
.rw_data_in
,
443 o_rw_data_out
= mi
.rw_data_out
,
444 o_rw_address_valid
= mi
.rw_address_valid
,
445 o_rw_wait
= mi
.rw_wait
,
446 o_tty_write
= self
.tty_write
,
447 o_tty_write_data
= self
.tty_write_data
,
448 i_tty_write_busy
= self
.tty_write_busy
,
449 i_switch_2
= self
.switch_2
,
450 i_switch_3
= self
.switch_3
,
451 o_led_1
= self
.led_1
,
456 ft
= Fetch(self
.comb
, self
.sync
)
458 fs
= Instance("CPUFetchStage", name
="fetch_stage",
461 o_memory_interface_fetch_address
= mi
.fetch_address
,
462 i_memory_interface_fetch_data
= mi
.fetch_data
,
463 i_memory_interface_fetch_valid
= mi
.fetch_valid
,
464 i_fetch_action
= ft
.action
,
465 i_target_pc
= ft
.target_pc
,
466 o_output_pc
= ft
.output_pc
,
467 o_output_instruction
= ft
.output_instruction
,
468 o_output_state
= ft
.output_state
,
469 i_reset_vector
= reset_vector
,
476 cd
= Instance("CPUDecoder", name
="decoder",
477 i_instruction
= ft
.output_instruction
,
478 o_funct7
= dc
.funct7
,
479 o_funct3
= dc
.funct3
,
483 o_immediate
= dc
.immediate
,
484 o_opcode
= dc
.opcode
,
485 o_decode_action
= dc
.act
489 self
.comb
+= self
.regs
.rs_a
.eq(dc
.rs1
)
490 self
.comb
+= self
.regs
.rs_b
.eq(dc
.rs2
)
492 load_store_address
= Signal(32)
493 load_store_address_low_2
= Signal(2)
494 load_store_misaligned
= Signal()
495 unmasked_loaded_value
= Signal(32)
496 loaded_value
= Signal(32)
498 lsc
= Instance("CPULoadStoreCalc", name
="cpu_loadstore_calc",
499 i_dc_immediate
= dc
.immediate
,
500 i_dc_funct3
= dc
.funct3
,
501 i_rs1
= self
.regs
.rs1
,
502 i_rs2
= self
.regs
.rs2
,
503 i_rw_data_in
= mi
.rw_data_in
,
504 i_rw_data_out
= mi
.rw_data_out
,
505 o_load_store_address
= load_store_address
,
506 o_load_store_address_low_2
= load_store_address_low_2
,
507 o_load_store_misaligned
= load_store_misaligned
,
508 o_loaded_value
= loaded_value
)
512 # XXX rwaddr not 31:2 any more
513 self
.comb
+= mi
.rw_address
.eq(load_store_address
[2:])
515 unshifted_load_store_byte_mask
= Signal(4)
517 self
.comb
+= unshifted_load_store_byte_mask
.eq(self
.get_lsbm(dc
))
519 # XXX yuck. this will cause migen simulation to fail
520 # (however conversion to verilog works)
521 self
.comb
+= mi
.rw_byte_mask
.eq(
522 _Operator("<<", [unshifted_load_store_byte_mask
,
523 load_store_address_low_2
]))
525 self
.comb
+= mi
.rw_active
.eq(~self
.reset
526 & (ft
.output_state
== FOS
.valid
)
527 & ~load_store_misaligned
528 & ((dc
.act
& (DA
.load | DA
.store
)) != 0))
530 self
.comb
+= mi
.rw_read_not_write
.eq(~dc
.opcode
[5])
535 alu_result
= Signal(32)
537 self
.comb
+= alu_a
.eq(self
.regs
.rs1
)
538 self
.comb
+= alu_b
.eq(Mux(dc
.opcode
[5],
542 ali
= Instance("cpu_alu", name
="alu",
543 i_funct7
= dc
.funct7
,
544 i_funct3
= dc
.funct3
,
545 i_opcode
= dc
.opcode
,
548 o_result
= alu_result
552 lui_auipc_result
= Signal(32)
553 self
.comb
+= lui_auipc_result
.eq(Mux(dc
.opcode
[5],
555 dc
.immediate
+ ft
.output_pc
))
557 self
.comb
+= ft
.target_pc
.eq(Cat(0,
558 Mux(dc
.opcode
!= OP
.jalr
,
560 self
.regs
.rs1
[1:32] + dc
.immediate
[1:32])))
562 misaligned_jump_target
= Signal()
563 self
.comb
+= misaligned_jump_target
.eq(ft
.target_pc
[1])
565 branch_arg_a
= Signal(32)
566 branch_arg_b
= Signal(32)
567 self
.comb
+= branch_arg_a
.eq(Cat( self
.regs
.rs1
[0:31],
568 self
.regs
.rs1
[31] ^ ~dc
.funct3
[1]))
569 self
.comb
+= branch_arg_b
.eq(Cat( self
.regs
.rs2
[0:31],
570 self
.regs
.rs2
[31] ^ ~dc
.funct3
[1]))
572 branch_taken
= Signal()
573 self
.comb
+= branch_taken
.eq(dc
.funct3
[0] ^
575 branch_arg_a
< branch_arg_b
,
576 branch_arg_a
== branch_arg_b
))
578 m
= M(self
.comb
, self
.sync
)
579 mstatus
= MStatus(self
.comb
, self
.sync
)
580 mie
= MIE(self
.comb
, self
.sync
)
581 misa
= Misa(self
.comb
, self
.sync
)
584 mp
= Instance("CPUMIP", name
="cpu_mip",
589 mii
= Instance("CPUMIE", name
="cpu_mie",
597 ms
= Instance("CPUMStatus", name
="cpu_mstatus",
598 o_mstatus
= mstatus
.mstatus
,
599 i_mpie
= mstatus
.mpie
,
605 csr
= CSR(self
.comb
, self
.sync
, dc
, self
.regs
.rs1
)
607 fi
= Instance("CPUFetchAction", name
="cpu_fetch_action",
608 o_fetch_action
= ft
.action
,
609 i_output_state
= ft
.output_state
,
611 i_load_store_misaligned
= load_store_misaligned
,
612 i_mi_rw_wait
= mi
.rw_wait
,
613 i_mi_rw_address_valid
= mi
.rw_address_valid
,
614 i_branch_taken
= branch_taken
,
615 i_misaligned_jump_target
= misaligned_jump_target
,
616 i_csr_op_is_valid
= csr
.op_is_valid
)
620 minfo
= MInfo(self
.comb
)
622 self
.handle_trap
= Signal(reset
=0)
624 ht
= Instance("CPUHandleTrap", "cpu_handle_trap",
625 i_ft_action
= ft
.action
,
626 i_ft_output_pc
= ft
.output_pc
,
627 i_dc_action
= dc
.act
,
628 i_dc_immediate
= dc
.immediate
,
629 i_load_store_misaligned
= load_store_misaligned
,
636 self
.sync
+= If(~self
.reset
,
637 self
.main_block(mtvec
, mip
, minfo
, misa
, csr
, mi
, m
,
638 mstatus
, mie
, ft
, dc
,
639 load_store_misaligned
,
645 if __name__
== "__main__":
647 print(verilog
.convert(example
,
650 example
.tty_write_data
,
651 example
.tty_write_busy
,