debug_rom/debug_rom.S

   1 # This code should be functional. Doesn't have to be optimal.
   2 # I'm writing it to prove that it can be done.
   3
   4 # TODO: Update these constants once they're finalized in the doc.
   5
   6 #define DCSR                    0x790
   7 #define DCSR_CAUSE_DEBINT       3
   8 #define DCSR_HALT_OFFSET        3
   9 #define DCSR_DEBUGINT_OFFSET    10
  10
  11 #define DSCRATCH                0x792
  12
  13 #define MCPUID                  0xf00
  14 #define MHARTID                 0xf10
  15
  16 # TODO: Should be 0x400
  17 #define DEBUG_RAM               (-0x400)
  18 #define DEBUG_RAM_SIZE          64
  19
  20 #define SETHALTNOT              0x100
  21 #define CLEARHALTNOT            0x104
  22 #define CLEARDEBINT             0x108
  23
  24         .global entry
  25         .global resume
  26
  27         # Automatically called when Debug Mode is first entered.
  28 entry:  j       _entry
  29         # Should be called by Debug RAM code that has finished execution and
  30         # wants to return to Debug Mode.
  31 resume:
  32         # Clear debug interrupt.
  33 clear_debint:
  34         csrr    s1, MHARTID
  35         sw      s1, CLEARDEBINT(zero)
  36 clear_debint_loop:
  37         csrr    s1, DCSR
  38         andi    s1, s1, (1<<DCSR_DEBUGINT_OFFSET)
  39         bnez    s1, wait_for_interrupt
  40
  41         # Restore s1.
  42         csrr    s1, MCPUID
  43         bltz    s1, restore_not_32
  44 restore_32:
  45         lw      s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 4)(zero)
  46         j       check_halt
  47 restore_not_32:
  48         slli    s1, s1, 1
  49         bltz    s1, restore_128
  50 restore_64:
  51         ld      s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 8)(zero)
  52         j       check_halt
  53 restore_128:
  54         nop     #lq      s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 16)(zero)
  55
  56 check_halt:
  57         csrr    s0, DCSR
  58         andi    s0, s0, (1<<DCSR_HALT_OFFSET)
  59         beqz    s0, exit
  60         j       wait_for_interrupt
  61
  62 exit:
  63         # Restore s0.
  64         csrr    s0, DSCRATCH
  65         eret
  66
  67
  68 _entry:
  69         # Save s0 in DSCRATCH
  70         csrw    DSCRATCH, s0
  71
  72         # Check why we're here
  73         csrr    s0, DCSR
  74         # cause is in bits 2:0 of dcsr
  75         andi    s0, s0, 7
  76         addi    s0, s0, -DCSR_CAUSE_DEBINT
  77         bnez    s0, spontaneous_halt
  78
  79 jdebugram:
  80         # Save s1 so that the debug program can use two registers.
  81         csrr    s0, MCPUID
  82         bltz    s0, save_not_32
  83 save_32:
  84         sw      s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 4)(zero)
  85         jr      zero, DEBUG_RAM
  86 save_not_32:
  87         slli    s0, s0, 1
  88         bltz    s0, save_128
  89 save_64:
  90         sd      s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 8)(zero)
  91         jr      zero, DEBUG_RAM
  92 save_128:
  93         nop     #sq      s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 16)(zero)
  94         jr      zero, DEBUG_RAM
  95
  96 spontaneous_halt:
  97         csrr    s0, MHARTID
  98         sw      s0, SETHALTNOT(zero)
  99         csrsi   DCSR, DCSR_HALT_OFFSET
 100
 101 wait_for_interrupt:
 102         csrr    s0, DCSR
 103         andi    s0, s0, (1<<DCSR_DEBUGINT_OFFSET)
 104         beqz    s0, wait_for_interrupt
 105
 106         j       jdebugram