debug_rom/debug_rom.S

   1 // See LICENSE.SiFive for license details.
   2
   3 #include "spike/encoding.h"
   4
   5 // These are implementation-specific addresses in the Debug Module
   6 #define HALTED    0x100
   7 #define GOING     0x104
   8 #define RESUMING  0x108
   9 #define EXCEPTION 0x10C
  10
  11 // Region of memory where each hart has 1
  12 // byte to read.
  13 #define FLAGS 0x400
  14 #define FLAG_GO     0
  15 #define FLAG_RESUME 1
  16
  17         .option norvc
  18         .global entry
  19         .global exception
  20
  21         // Entry location on ebreak, Halt, or Breakpoint
  22         // It is the same for all harts. They branch when
  23         // their GO or RESUME bit is set.
  24
  25 entry:
  26        jal zero, _entry
  27 resume:
  28        jal zero, _resume
  29 exception:
  30        jal zero, _exception
  31
  32 _entry:
  33         // This fence is required because the execution may have written something
  34         // into the Abstract Data or Program Buffer registers.
  35         fence
  36         csrw CSR_DSCRATCH, s0  // Save s0 to allow signaling MHARTID
  37
  38         // We continue to let the hart know that we are halted in order that
  39         // a DM which was reset is still made aware that a hart is halted.
  40         // We keep checking both whether there is something the debugger wants
  41         // us to do, or whether we should resume.
  42 entry_loop:
  43         csrr s0, CSR_MHARTID
  44         sw   s0, HALTED(zero)
  45         lbu  s0, FLAGS(s0) // 1 byte flag per hart. Only one hart advances here.
  46         andi s0, s0, (1 << FLAG_GO)
  47         bnez s0, going
  48         csrr s0, CSR_MHARTID
  49         lbu  s0, FLAGS(s0) // multiple harts can resume  here
  50         andi s0, s0, (1 << FLAG_RESUME)
  51         bnez s0, resume
  52         jal  zero, entry_loop
  53
  54 _exception:
  55         sw      zero, EXCEPTION(zero) // Let debug module know you got an exception.
  56         ebreak
  57
  58 going:
  59         csrr s0, CSR_DSCRATCH          // Restore s0 here
  60         sw zero, GOING(zero)           // When debug module sees this write, the GO flag is reset.
  61         jalr zero, zero, %lo(whereto)          // Rocket-Chip has a specific hack which is that jalr in
  62                                        // Debug Mode will flush the I-Cache. We need that so that the
  63                                        // remainder of the variable instructions will be what Debug Module
  64                                        // intends.
  65 _resume:
  66         csrr s0, CSR_MHARTID
  67         sw   s0, RESUMING(zero) // When Debug Module sees this write, the RESUME flag is reset.
  68         csrr s0, CSR_DSCRATCH   // Restore s0
  69         dret
  70
  71         // END OF ACTUAL "ROM" CONTENTS. BELOW IS JUST FOR LINKER SCRIPT.
  72
  73 .section .whereto
  74 whereto:
  75         nop
  76         // Variable "ROM" This is : jal x0 abstract, jal x0 program_buffer,
  77         //                or jal x0 resume, as desired.
  78         //                Debug Module state machine tracks what is 'desired'.
  79         //                We don't need/want to use jalr here because all of the
  80         //                Variable ROM contents are set by
  81         //                Debug Module before setting the OK_GO byte.