hwacha/decode_hwacha.h

   1 #ifndef _DECODE_HWACHA_H
   2 #define _DECODE_HWACHA_H
   3
   4 #include "hwacha.h"
   5 #include "hwacha_xcpt.h"
   6
   7 #define XS1 (xs1)
   8 #define XS2 (xs2)
   9 #define WRITE_XRD(value) (xd = value)
  10
  11 #define NXPR (h->get_ct_state()->nxpr)
  12 #define NFPR (h->get_ct_state()->nfpr)
  13 #define MAXVL (h->get_ct_state()->maxvl)
  14 #define VL (h->get_ct_state()->vl)
  15 #define UTIDX (h->get_ct_state()->count)
  16 #define VF_PC (h->get_ct_state()->vf_pc)
  17 #define WRITE_NXPR(nxprnext) (h->get_ct_state()->nxpr = (nxprnext))
  18 #define WRITE_NFPR(nfprnext) (h->get_ct_state()->nfpr = (nfprnext))
  19 #define WRITE_MAXVL(maxvlnext) (h->get_ct_state()->maxvl = (maxvlnext))
  20 #define WRITE_VL(vlnext) (h->get_ct_state()->vl = (vlnext))
  21 #define WRITE_UTIDX(value) (h->get_ct_state()->count = (value))
  22 #define WRITE_VF_PC(pcnext) (h->get_ct_state()->vf_pc = (pcnext))
  23 #define WRITE_PREC(precision) (h->get_ct_state()->prec = (precision))
  24
  25 #define INSN_RS1 (insn.rs1())
  26 #define INSN_RS2 (insn.rs2())
  27 #define INSN_RS3 (insn.rs3())
  28 #define INSN_RD (insn.rd())
  29 #define INSN_SEG (((reg_t)insn.i_imm() >> 9)+1)
  30
  31 static inline reg_t read_xpr(hwacha_t* h, insn_t insn, uint32_t idx, size_t src)
  32 {
  33   if (src >= h->get_ct_state()->nxpr)
  34     h->take_exception(HWACHA_CAUSE_TVEC_ILLEGAL_REGID, insn.bits());
  35   return (h->get_ut_state(idx)->XPR[src]);
  36 }
  37
  38 static inline void write_xpr(hwacha_t* h, insn_t insn, uint32_t idx, size_t dst, reg_t value)
  39 {
  40   if (dst >= h->get_ct_state()->nxpr)
  41     h->take_exception(HWACHA_CAUSE_TVEC_ILLEGAL_REGID, insn.bits());
  42   h->get_ut_state(idx)->XPR.write(dst, value);
  43 }
  44
  45 #define UT_READ_XPR(idx, src) read_xpr(h, insn, idx, src)
  46 #define UT_WRITE_XPR(idx, dst, value) write_xpr(h, insn, idx, dst, value)
  47 #define UT_RS1(idx) (UT_READ_XPR(idx, INSN_RS1))
  48 #define UT_RS2(idx) (UT_READ_XPR(idx, INSN_RS2))
  49 #define UT_WRITE_RD(idx, value) (UT_WRITE_XPR(idx, INSN_RD, value))
  50
  51 static inline reg_t read_fpr(hwacha_t* h, insn_t insn, uint32_t idx, size_t src)
  52 {
  53   if (src >= h->get_ct_state()->nfpr)
  54     h->take_exception(HWACHA_CAUSE_TVEC_ILLEGAL_REGID, insn.bits());
  55   return (h->get_ut_state(idx)->FPR[src]);
  56 }
  57
  58 static inline void write_fpr(hwacha_t* h, insn_t insn, uint32_t idx, size_t dst, reg_t value)
  59 {
  60   if (dst >= h->get_ct_state()->nfpr)
  61     h->take_exception(HWACHA_CAUSE_TVEC_ILLEGAL_REGID, insn.bits());
  62   h->get_ut_state(idx)->FPR.write(dst, value);
  63 }
  64
  65 #define UT_READ_FPR(idx, src) read_fpr(h, insn, idx, src)
  66 #define UT_WRITE_FPR(idx, dst, value) write_fpr(h, insn, idx, dst, value)
  67 #define UT_FRS1(idx) (UT_READ_FPR(idx, INSN_RS1))
  68 #define UT_FRS2(idx) (UT_READ_FPR(idx, INSN_RS2))
  69 #define UT_FRS3(idx) (UT_READ_FPR(idx, INSN_RS3))
  70 #define UT_WRITE_FRD(idx, value) (UT_WRITE_FPR(idx, INSN_RD, value))
  71
  72 #define VEC_SEG_LOAD(dst, func, inc) \
  73   VEC_SEG_ST_LOAD(dst, func, INSN_SEG*inc, inc)
  74
  75 #define VEC_SEG_ST_LOAD(dst, func, stride, inc) \
  76   reg_t seg_addr = XS1; \
  77   for (uint32_t i=0; i<VL; i++) { \
  78     reg_t addr = seg_addr; \
  79     seg_addr += stride; \
  80     for (uint32_t j=0; j<INSN_SEG; j++) { \
  81       UT_WRITE_##dst(i, INSN_RD+j, p->get_mmu()->func(addr)); \
  82       addr += inc; \
  83     } \
  84   }
  85
  86 #define VEC_SEG_STORE(src, func, inc) \
  87   VEC_SEG_ST_STORE(src, func, INSN_SEG*inc, inc)
  88
  89 #define VEC_SEG_ST_STORE(src, func, stride, inc) \
  90   reg_t seg_addr = XS1; \
  91   for (uint32_t i=0; i<VL; i++) { \
  92     reg_t addr = seg_addr; \
  93     seg_addr += stride; \
  94     for (uint32_t j=0; j<INSN_SEG; j++) { \
  95       p->get_mmu()->func(addr, UT_READ_##src(i, INSN_RD+j)); \
  96       addr += inc; \
  97     } \
  98   }
  99
 100 #define require_supervisor_hwacha \
 101   if (unlikely(!(p->get_state()->sr & SR_S))) \
 102     h->take_exception(HWACHA_CAUSE_PRIVILEGED_INSTRUCTION, insn.bits());
 103
 104 #endif