hwacha/hwacha.h

   1 #ifndef _HWACHA_H
   2 #define _HWACHA_H
   3
   4 // vector stuff
   5 #define VL vl
   6
   7 #define UT_RS1(idx) uts[idx]->XPR[insn.rtype.rs1]
   8 #define UT_RS2(idx) uts[idx]->XPR[insn.rtype.rs2]
   9 #define UT_RD(idx) uts[idx]->XPR.write_port(insn.rtype.rd)
  10 #define UT_RA(idx) uts[idx]->XPR.write_port(1)
  11 #define UT_FRS1(idx) uts[idx]->FPR[insn.ftype.rs1]
  12 #define UT_FRS2(idx) uts[idx]->FPR[insn.ftype.rs2]
  13 #define UT_FRS3(idx) uts[idx]->FPR[insn.ftype.rs3]
  14 #define UT_FRD(idx) uts[idx]->FPR.write_port(insn.ftype.rd)
  15 #define UT_RM(idx) ((insn.ftype.rm != 7) ? insn.ftype.rm : \
  16               ((uts[idx]->fsr & FSR_RD) >> FSR_RD_SHIFT))
  17
  18 #define UT_LOOP_START for (int i=0;i<VL; i++) {
  19 #define UT_LOOP_END }
  20 #define UT_LOOP_RS1 UT_RS1(i)
  21 #define UT_LOOP_RS2 UT_RS2(i)
  22 #define UT_LOOP_RD UT_RD(i)
  23 #define UT_LOOP_RA UT_RA(i)
  24 #define UT_LOOP_FRS1 UT_FRS1(i)
  25 #define UT_LOOP_FRS2 UT_FRS2(i)
  26 #define UT_LOOP_FRS3 UT_FRS3(i)
  27 #define UT_LOOP_FRD UT_FRD(i)
  28 #define UT_LOOP_RM UT_RM(i)
  29
  30 #define VEC_LOAD(dst, func, inc) \
  31   reg_t addr = RS1; \
  32   UT_LOOP_START \
  33     UT_LOOP_##dst = mmu.func(addr); \
  34     addr += inc; \
  35   UT_LOOP_END
  36
  37 #define VEC_STORE(src, func, inc) \
  38   reg_t addr = RS1; \
  39   UT_LOOP_START \
  40     mmu.func(addr, UT_LOOP_##src); \
  41     addr += inc; \
  42   UT_LOOP_END
  43
  44 enum vt_command_t
  45 {
  46   vt_command_stop,
  47 };
  48
  49 #endif