add hwacha exception support
[riscv-isa-sim.git] / hwacha / insns / vf.h
1 if (VL) {
2 if (!h->vf_active()) {
3 WRITE_VF_PC(XS1 + insn.s_imm());
4 for (uint32_t i=0; i<VL; i++)
5 h->get_ut_state(i)->run = true;
6 }
7
8 if (VF_PC & 3)
9 h->take_exception(HWACHA_CAUSE_VF_MISALIGNED_FETCH, VF_PC);
10
11 mmu_t::insn_fetch_t ut_fetch = p->get_mmu()->load_insn(VF_PC);
12 insn_t ut_insn = ut_fetch.insn.insn;
13
14 bool matched = false;
15
16 #define DECLARE_INSN(name, match, mask) \
17 extern reg_t hwacha_##name(processor_t*, insn_t, reg_t); \
18 if ((ut_insn.bits() & mask) == match) { \
19 WRITE_VF_PC(hwacha_##name(p, ut_insn, VF_PC)); \
20 matched = true; \
21 }
22 #include "opcodes_hwacha_ut.h"
23 #undef DECLARE_INSN
24
25 if (!matched)
26 h->take_exception(HWACHA_CAUSE_VF_ILLEGAL_INSTRUCTION, VF_PC);
27
28 // if vf is still running, rewind pc so that it will execute again
29 if (h->vf_active())
30 npc = pc;
31 }