id_regs.py

   1 #!/usr/bin/env python
   2 # Copyright (C) 2018 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   3
   4 """ identify registers used in riscv/insns/*.h and create code
   5     that can be used in spike at runtime
   6
   7     the design of spike assumes that once an opcode is identified,
   8     the role of decoding the instruction is implicitly rolled into
   9     and included inside the function that emulates that opcode.
  10
  11     however there may be circumstances where the behaviour of an
  12     instruction has to change depending on "tags" associated with
  13     the registers (security extensions, simple-v extension).
  14
  15     therefore this code walks the instruction implementations
  16     in riscv/insns/*.h looking for register usage patterns.
  17     the resultant table can be used *prior* to the emulation,
  18     without having to manually maintain such a table.
  19 """
  20
  21 import os
  22 import sys
  23
  24 insns_dir = "./riscv/insns"
  25 def list_insns():
  26     if len(sys.argv) == 2:
  27         fullfname = sys.argv[1]
  28         pth, fname = os.path.split(fullfname)
  29         insn = fname[:-2]
  30         return [(fullfname, insn)]
  31
  32     res = []
  33     for fname in os.listdir(insns_dir):
  34         if not fname.endswith(".h"):
  35             continue
  36         if fname.startswith("regs_"):
  37             continue
  38         insn = fname[:-2]
  39         res.append((os.path.join(insns_dir, fname), insn))
  40     return res
  41
  42 cintpatterns = [ 'WRITE_RVC_RS1S', 'WRITE_RVC_RS2S',
  43                  'RVC_RS1', 'RVC_RS2', 'RVC_RS1S', 'RVC_RS2S', ]
  44 cfloatpatterns = [ 'WRITE_RVC_FRS2S', 'RVC_FRS2 ', 'RVC_FRS2S ']
  45 intpatterns   = ['WRITE_RD' , 'RS1', 'RS2', 'RS3']
  46 floatpatterns = ['WRITE_FRD', 'FRS1', 'FRS2', 'FRS3']
  47 patterns = intpatterns + floatpatterns
  48 patterns += cintpatterns
  49 patterns += cfloatpatterns
  50
  51 allfloats = floatpatterns + cfloatpatterns
  52 floatmask = (1<<len(allfloats)-1)
  53 allints = intpatterns + cintpatterns[2:]
  54
  55 skip = '#define USING_NOREGS\n' \
  56        '#define REGS_PATTERN 0x0\n'
  57 def find_registers(fname):
  58     # HACK! macro-skipping of instructions too painful
  59     for notparallel in ['csr', 'lui', 'c_j', 'wfi', 'auipc',
  60                         'dret', 'uret', 'mret', 'sret']:
  61         if notparallel in fname:
  62             return skip
  63     res = []
  64     isintfloat = 0x0 + floatmask << len(allints)
  65     with open(fname) as f:
  66         f = f.read()
  67         for pattern in patterns:
  68             x = f.find(pattern)
  69             if x == -1:
  70                 continue
  71             if pattern.startswith('R') and x != 0 and f[x-1] == 'F':
  72                 # botch-job/hack: RS1 also matches against FRS1 (etc.)
  73                 # check letter before match: if "F", skip it.
  74                 continue
  75             if pattern.startswith('R') and x != 0 and f[x-1] == '_':
  76                 # RS1 also matches against RVC_RS1 (etc.)
  77                 # check letter before match: if "_", skip it.
  78                 continue
  79             if pattern.startswith('FR') and x != 0 and f[x-1] == '_':
  80                 # RS1 also matches against RVC_FRS1 (etc.)
  81                 # check letter before match: if "_", skip it.
  82                 continue
  83             if 'RVC_' in pattern and f[x+len(pattern)] == 'S':
  84                 # RVC_RS2S also matches against RVC_RS2 (etc.)
  85                 # check letter at end of match: if "S", skip it.
  86                 continue
  87             p = pattern
  88             if p.startswith('WRITE_'):
  89                 p = p[6:]
  90             if pattern in allints:
  91                 idx = allints.index(pattern)
  92                 isintfloat += 1 << idx
  93             if pattern in allfloats:
  94                 idx = allfloats.index(pattern)
  95                 isintfloat &= ~(1 << (idx+len(allints)))
  96             res.append('#define USING_REG_%s' % p)
  97     if not res:
  98         return skip
  99     res.append('#define REGS_PATTERN 0x%x' % isintfloat)
 100     return '\n'.join(res)
 101
 102 if __name__ == '__main__':
 103     files = list_insns()
 104     for (fname, insn) in files:
 105         regsname = "regs_%s.h" % insn
 106         regsname = os.path.join(insns_dir, regsname)
 107         with open(regsname, "w") as f:
 108             txt = find_registers(fname)
 109             txt += "\n#define INSN_%s\n" % insn.upper()
 110             # help identify type of register
 111             if insn in ['beq', 'bne', 'blt', 'bltu', 'bge', 'bgeu']:
 112                 txt += "#define INSN_TYPE_BRANCH\n"
 113             elif insn in ['c_ld', 'c_bnez']:
 114                 txt += "\n#define INSN_TYPE_C_BRANCH\n"
 115             elif insn in ['c_lwsp', 'c_ldsp', 'c_lqsp', 'c_flwsp', 'c_fldsp']:
 116                 txt += "\n#define INSN_TYPE_C_STACK_LD\n"
 117             elif insn in ['c_swsp', 'c_sdsp', 'c_sqsp', 'c_fswsp', 'c_fsdsp']:
 118                 txt += "\n#define INSN_TYPE_C_STACK_ST\n"
 119             elif insn in ['c_lw', 'c_ld', 'c_lq', 'c_flw', 'c_fld']:
 120                 txt += "\n#define INSN_TYPE_C_LD\n"
 121             elif insn in ['c_sw', 'c_sd', 'c_sq', 'c_fsw', 'c_fsd']:
 122                 txt += "\n#define INSN_TYPE_C_ST\n"
 123             elif insn in ['c_beqz', 'c_bnez']:
 124                 txt += "\n#define INSN_TYPE_C_BRANCH\n"
 125             elif insn.startswith("c_"):
 126                 txt += "#define INSN_TYPE_C\n"
 127             elif insn.startswith("fmv") or \
 128                  insn.startswith("fcvt") or \
 129                  insn.startswith("fsgn"):
 130                 txt += "#define INSN_TYPE_FP_DUALOP\n"
 131             elif insn.startswith("feq") or \
 132                  insn.startswith("flt") or \
 133                  insn.startswith("fle"):
 134                 txt += "#define INSN_TYPE_FP_BRANCH\n"
 135             f.write(txt)