openpower/sv/po9_encoding.mdwn

   1 # Definitions
   2
   3 **Proposal: Add the following Definition to Section 1.3.1 of Book I**
   4
   5 **Definition of SVP64 Prefixing:**
   6
   7 In its simpest form, SVP64 is a 32-bit Prefix conceptually similar to Intel 8086 `REP`
   8 instruction that both augments its following Defined Word Suffix, and also may
   9 repeat that instruction with optional sequential register offsets from those given in the
  10 Suffix. Register numbers may also be extended (larger register files).
  11 More advanced features add predication, element-width overrides, and Vertical-First
  12 Mode.
  13
  14 **Definition of Vertical-First:**
  15
  16 Normal Cray-style Vectorisation, designated Horizontal-First, performs element-level
  17 operations (often in parallel) before moving in the usual fashion to the next
  18 instruction. Vertical-First on the other hand executes *one element operation only*
  19 then moves on to the next instruction, whereupon if that is also an SVP64-Prefixed
  20 instruction the exact same element offset is used.  Element offsets are then explicitly
  21 advanced by calling a special instruction, `svstep`. The term "Vertical-First"
  22 stems from visually listing program instructions vertically and register files horizontally.
  23
  24 **Definition of SVP64Single Prefixing:**
  25
  26 A 32-bit Prefix in front of a Defined Word that extends register numbers
  27 (allows larger register files), adds single-bit predication, element-width overrides,
  28 and optionally adds Saturation to Arithmetic instructions that normally would not
  29 have it.  *SVP64 is in Draft only* and is yet to be defined.
  30
  31 **Definition of "UnVectoriseable":**
  32
  33 Any operation that inherently makes no sense if repeated (through SVP64
  34 Prefixing) is termed "UnVectoriseable" or "UnVectorised".  Examples
  35 include `sc` or `sync` which have no registers. `mtmsr` is also classed
  36 as UnVectoriseable because there is only one `MSR`.
  37
  38 UnVectorised instructions are required to be detected as such if
  39 Prefixed (either SVP64 or SVP64Single) and an Illegal Instruction
  40 Trap raised.
  41
  42 *Architectural Note: Given that a "pre-classification" Decode Phase is
  43 required (identifying whether the Suffix - Defined Word - is
  44 Arithmetic/Logical, CR-op, Load/Store or Branch-Conditional),
  45 adding "UnVectorised" to this phase is not unreasonable.*
  46
  47 # New 64-bit Instruction Encoding spaces
  48
  49 **Proposal: Add new Section 1.6.5 to Book I**
  50
  51 The following seven new areas are defined within Primary Opcode 9 (EXT009)
  52 as a new 64-bit encoding space, alongside Primary Opcode 1
  53 (EXT1xx).
  54
  55 | 0-5 | 6 | 7 | 8-31  | 32| Description                        |
  56 |-----|---|---|-------|---|------------------------------------|
  57 | PO  | 0 | x | xxxx  | 0 | `RESERVED2` (57-bit) |
  58 | PO  | 0 | 0 | !zero | 1 | SVP64Single:EXT232-263, or `RESERVED3` |
  59 | PO  | 0 | 0 | 0000  | 1 | Scalar EXT232-263               |
  60 | PO  | 0 | 1 | nnnn  | 1 | SVP64:EXT232-263     |
  61 | PO  | 1 | 0 | 0000  | x | `RESERVED1` (32-bit) |
  62 | PO  | 1 | 0 | !zero | n | SVP64Single:EXT000-063 or `RESERVED4` |
  63 | PO  | 1 | 1 | nnnn  | n | SVP64:EXT000-063       |
  64
  65 Note that for the future SVP64Single Encoding (currently RESERVED3 and 4)
  66 it is prohibited to have bits 8-31 be zero, unlike for SVP64 Vector space,
  67 for which bits 8-31 can be zero (termed `scalar identity behaviour`). This
  68 prohibition allows SVP64Single to share its Encoding space with Scalar
  69 Ext232-263 and Scalar EXT300-363.
  70
  71 Also that RESERVED1 and 2 are candidates for future Major opcode
  72 areas EXT200-231 and EXT300-363 respectively, however as RESERVED areas
  73 they may equally be allocated entirely differently.
  74
  75 *Architectural Resource Allocation Note: **under no circumstances** must
  76 different Defined Words be allocated within any `EXT{z}` prefixed or
  77 unprefixed space for a given value of `z` of 0, 2 or 3. Even if UnVectoriseable
  78 an instruction Defined Word space must have the exact same Instruction
  79 and exact same Instruction Encoding in all spaces being RESERVED (Illegal
  80 Instruction Trap if UnVectoriseable) or not be allocated at all.
  81 This is required as an inviolate hard rule governing Primary Opcode 9
  82 that may not be revoked under any circumstances. A useful way to think
  83 of this is that the Prefix Encoding is, like the 8086 REP instruction,
  84 an independent 32-bit Defined Word. The only semi-exceptions are
  85 the Post-Increment Mode of LD/ST-Update and Vectorised Branch-Conditional.*
  86
  87 Encoding spaces and their potential are illustrated:
  88
  89 | Encoding |Available bits|Scalar|Vectoriseable | SVP64Single  | PO1-Prefixable |
  90 |----------|--------------|------|--------------|--------------|----------------|
  91 |EXT000-063| 32           | yes  | yes          |yes           |yes             |
  92 |EXT100-163| 64           | yes  | no           |no            |not twice       |
  93 |RESERVED2 | 57           | N/A  |not applicable|not applicable|not applicable  |
  94 |EXT232-263| 32           | yes  | yes          |yes           |no              |
  95 |RESERVED1 | 32           | N/A  | no           |no            |no              |
  96
  97 Notes:
  98
  99 * Prefixed-Prefixed (96-bit) instructions are prohibited. EXT1xx is
 100   thus inherently UnVectoriseable as the EXT1xx prefix is 32-bit
 101   on top of an SVP64 prefix which is 32-bit on top of a Defined Word
 102   and the complexity at the Decoder becomes too great for High
 103   Performance Multi-Issue systems.
 104 * EXT100-163 instructions (PO1-Prefixed) are also prohibited from being
 105   double-PO1-prefixed (not twice prefixed)
 106 * RESERVED2 presently remains unallocated as of yet and therefore its
 107   potential is not yet defined (Not Applicable).
 108 * RESERVED1 is also unallocated at present, but it is known in advance
 109   that the area is UnVectoriseable and also cannot be Prefixed with
 110   SVP64Single.
 111 * Considerable care is needed both on Architectural Resource Allocation
 112   as well as instruction design itself.  Once an instruction is allocated
 113   in an UnVectoriseable area it can never be Vectorised without providing
 114   an entirely new Encoding.
 115
 116 [[!tag standards]]
 117
 118 --------
 119
 120 \newpage{}
 121