3 # DRAFT SVP64 for Power ISA v3.0B
5 * **DRAFT STATUS v0.1 18sep2021** Release notes <https://bugs.libre-soc.org/show_bug.cgi?id=699>
7 This document describes [[SV|sv]] augmentation of the [[Power|openpower]] v3.0B [[ISA|openpower/isa/]]. It is in Draft Status and
8 will be submitted to the [[!wikipedia OpenPOWER_Foundation]] ISA WG
9 via the External RFC Process.
11 Credits and acknowledgements:
19 * NLnet Foundation, for funding
20 * OpenPOWER Foundation
23 * IBM for the Power ISA itself
27 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001498.html>>
28 * [[svp64/discussion]]
30 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001650.html>
31 * <https://bugs.libre-soc.org/show_bug.cgi?id=550>
32 * <https://bugs.libre-soc.org/show_bug.cgi?id=573> TODO elwidth "infinite" discussion
33 * <https://bugs.libre-soc.org/show_bug.cgi?id=574> Saturating description.
34 * <https://bugs.libre-soc.org/show_bug.cgi?id=905> TODO [[sv/svp64-single]]
42 This document focuses on the encoding of [[SV|sv]], and assumes familiarity with the same. It does not cover how SV works (merely the instruction encoding), and is therefore best read in conjunction with the [[sv/overview]], as well as the [[sv/svp64_quirks]] section.
43 It is also crucial to note that whilst this format augments instruction
44 behaviour it works in conjunction with SVSTATE and other [[sv/sprs]].
46 All bit numbers are in MSB0 form (the bits are numbered from 0 at the MSB
48 and counting up as you move rightwards to the LSB end). All bit ranges are inclusive
49 (so `4:6` means bits 4, 5, and 6, in MSB0 order).
51 64-bit instructions are split into two 32-bit words, the prefix and the
52 suffix. The prefix always comes before the suffix in PC order.
54 | 0:5 | 6:31 | 32:63 |
55 |--------|--------------|--------------|
56 | EXT01 | v3.1 Prefix | v3.0/1 Suffix |
58 svp64 fits into the "reserved" portions of the v3.1 prefix, making it possible for svp64, v3.0B (or v3.1 including 64 bit prefixed) instructions to co-exist in the same binary without conflict.
60 Subset implementations in hardware are permitted, as long as certain
61 rules are followed, allowing for full soft-emulation including future
62 revisions. Details in the [[svp64/appendix]].
64 ## SVP64 encoding features
66 A number of features need to be compacted into a very small space of only 24 bits:
68 * Independent per-register Scalar/Vector tagging and range extension on every register
69 * Element width overrides on both source and destination
70 * Predication on both source and destination
71 * Two different sources of predication: INT and CR Fields
72 * SV Modes including saturation (for Audio, Video and DSP), mapreduce, fail-first and
73 predicate-result mode.
75 This document focusses specifically on how that fits into available space. The [[svp64/appendix]] explains more of the details, whilst the [[sv/overview]] gives the basics.
77 # Definition of Reserved in this spec.
79 For the new fields added in SVP64, instructions that have any of their
80 fields set to a reserved value must cause an illegal instruction trap,
81 to allow emulation of future instruction sets, or for subsets of SVP64
82 to be implemented in hardware and the rest emulated.
83 This includes SVP64 SPRs: reading or writing values which are not
84 supported in hardware must also raise illegal instruction traps
85 in order to allow emulation.
86 Unless otherwise stated, reserved values are always all zeros.
88 This is unlike OpenPower ISA v3.1, which in many instances does not require a trap if reserved fields are nonzero. Where the standard Power ISA definition
89 is intended the red keyword `RESERVED` is used.
91 # Scalar Identity Behaviour
93 SVP64 is designed so that when the prefix is all zeros, and
95 influence occurs (no augmentation) such that all standard Power ISA
96 v3.0/v3 1 instructions covered by the prefix are "unaltered". This is termed `scalar identity behaviour` (based on the mathematical definition for "identity", as in, "identity matrix" or better "identity transformation").
98 Note that this is completely different from when VL=0. VL=0 turns all operations under its influence into `nops` (regardless of the prefix)
99 whereas when VL=1 and the SV prefix is all zeros, the operation simply acts as if SV had not been applied at all to the instruction (an "identity transformation").
101 # Register Naming and size
103 SV Registers are simply the INT, FP and CR register files extended
104 linearly to larger sizes; SV Vectorisation iterates sequentially through these registers.
106 Where the integer regfile in standard scalar
107 Power ISA v3.0B/v3.1B is r0 to r31, SV extends this as r0 to r127.
108 Likewise FP registers are extended to 128 (fp0 to fp127), and CR Fields
110 extended to 128 entries, CR0 thru CR127.
112 The names of the registers therefore reflects a simple linear extension
113 of the Power ISA v3.0B / v3.1B register naming, and in hardware this
114 would be reflected by a linear increase in the size of the underlying
115 SRAM used for the regfiles.
117 Note: when an EXTRA field (defined below) is zero, SV is deliberately designed
118 so that the register fields are identical to as if SV was not in effect
119 i.e. under these circumstances (EXTRA=0) the register field names RA,
120 RB etc. are interpreted and treated as v3.0B / v3.1B scalar registers. This is part of
121 `scalar identity behaviour` described above.
125 With the way that EXTRA fields are defined and applied to register fields,
126 future versions of SV may involve 256 or greater registers. Backwards binary compatibility may be achieved with a PCR bit (Program Compatibility Register). Further discussion is out of scope for this version of SVP64.
128 # Remapped Encoding (`RM[0:23]`)
130 To allow relatively easy remapping of which portions of the Prefix Opcode
131 Map are used for SVP64 without needing to rewrite a large portion of the
132 SVP64 spec, a mapping is defined from the OpenPower v3.1 prefix bits to
133 a new 24-bit Remapped Encoding denoted `RM[0]` at the MSB to `RM[23]`
136 The mapping from the OpenPower v3.1 prefix bits to the Remapped Encoding
137 is defined in the Prefix Fields section.
139 ## Prefix Opcode Map (64-bit instruction encoding)
141 In the original table in the v3.1B Power ISA Spec on p1350, Table 12, prefix bits 6:11 are shown, with their allocations to different v3.1B pregix "modes".
143 The table below hows both PowerISA v3.1 instructions as well as new SVP instructions fit;
144 empty spaces are yet-to-be-allocated Illegal Instructions.
146 | 6:11 | ---000 | ---001 | ---010 | ---011 | ---100 | ---101 | ---110 | ---111 |
147 |------|--------|--------|--------|--------|--------|--------|--------|--------|
148 |000---| 8LS | 8LS | 8LS | 8LS | 8LS | 8LS | 8LS | 8LS |
149 |001---| | | | | | | | |
150 |010---| 8RR | | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
151 |011---| | | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
152 |100---| MLS | MLS | MLS | MLS | MLS | MLS | MLS | MLS |
153 |101---| | | | | | | | |
154 |110---| MRR | | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
155 |111---| | MMIRR | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`|
157 Note that by taking up a block of 16, where in every case bits 7 and 9 are set, this allows svp64 to utilise four bits of the v3.1B Prefix space and "allocate" them to svp64's Remapped Encoding field, instead.
161 To "activate" svp64 (in a way that does not conflict with v3.1B 64 bit Prefix mode), fields within the v3.1B Prefix Opcode Map are set
162 (see Prefix Opcode Map, above), leaving 24 bits "free" for use by SV.
163 This is achieved by setting bits 7 and 9 to 1:
165 | Name | Bits | Value | Description |
166 |------------|---------|-------|--------------------------------|
167 | EXT01 | `0:5` | `1` | Indicates Prefixed 64-bit |
168 | `RM[0]` | `6` | | Bit 0 of Remapped Encoding |
169 | SVP64_7 | `7` | `1` | Indicates this is SVP64 |
170 | `RM[1]` | `8` | | Bit 1 of Remapped Encoding |
171 | SVP64_9 | `9` | `1` | Indicates this is SVP64 |
172 | `RM[2:23]` | `10:31` | | Bits 2-23 of Remapped Encoding |
174 Laid out bitwise, this is as follows, showing how the 32-bits of the prefix
177 | 0:5 | 6 | 7 | 8 | 9 | 10:31 |
178 |--------|-------|---|-------|---|----------|
179 | EXT01 | RM | 1 | RM | 1 | RM |
180 | 000001 | RM[0] | 1 | RM[1] | 1 | RM[2:23] |
182 Following the prefix will be the suffix: this is simply a 32-bit v3.0B / v3.1
183 instruction. That instruction becomes "prefixed" with the SVP context: the
184 Remapped Encoding field (RM).
186 It is important to note that unlike v3.1 64-bit prefixed instructions
187 there is insufficient space in `RM` to provide identification of
188 any SVP64 Fields without first partially decoding the
189 32-bit suffix. Similar to the "Forms" (X-Form, D-Form) the
190 `RM` format is individually associated with every instruction.
192 Extreme caution and care must therefore be taken
193 when extending SVP64 in future, to not create unnecessary relationships
194 between prefix and suffix that could complicate decoding, adding latency.
198 The following fields are common to all Remapped Encodings:
200 | Field Name | Field bits | Description |
201 |------------|------------|----------------------------------------|
202 | MASKMODE | `0` | Execution (predication) Mask Kind |
203 | MASK | `1:3` | Execution Mask |
204 | SUBVL | `8:9` | Sub-vector length |
206 The following fields are optional or encoded differently depending
207 on context after decoding of the Scalar suffix:
209 | Field Name | Field bits | Description |
210 |------------|------------|----------------------------------------|
211 | ELWIDTH | `4:5` | Element Width |
212 | ELWIDTH_SRC | `6:7` | Element Width for Source |
213 | EXTRA | `10:18` | Register Extra encoding |
214 | MODE | `19:23` | changes Vector behaviour |
216 * MODE changes the behaviour of the SV operation (result saturation, mapreduce)
217 * SUBVL groups elements together into vec2, vec3, vec4 for use in 3D and Audio/Video DSP work
218 * ELWIDTH and ELWIDTH_SRC overrides the instruction's destination and source operand width
219 * MASK (and MASK_SRC) and MASKMODE provide predication (two types of sources: scalar INT and Vector CR).
220 * Bits 10 to 18 (EXTRA) are further decoded depending on the RM category for the instruction, which is determined only by decoding the Scalar 32 bit suffix.
222 Similar to Power ISA `X-Form` etc. EXTRA bits are given designations, such as `RM-1P-3S1D` which indicates for this example that the operation is to be single-predicated and that there are 3 source operand EXTRA tags and one destination operand tag.
224 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
228 Mode is an augmentation of SV behaviour. Different types of
229 instructions have different needs, similar to Power ISA
230 v3.1 64 bit prefix 8LS and MTRR formats apply to different
231 instruction types. Modes include Reduction, Iteration, arithmetic
232 saturation, and Fail-First. More specific details in each
233 section and in the [[svp64/appendix]]
235 * For condition register operations see [[sv/cr_ops]]
236 * For LD/ST Modes, see [[sv/ldst]].
237 * For Branch modes, see [[sv/branches]]
238 * For arithmetic and logical, see [[sv/normal]]
242 Default behaviour is set to 0b00 so that zeros follow the convention of
243 `scalar identity behaviour`. In this case it means that elwidth overrides
244 are not applicable. Thus if a 32 bit instruction operates on 32 bit,
245 `elwidth=0b00` specifies that this behaviour is unmodified. Likewise
246 when a processor is switched from 64 bit to 32 bit mode, `elwidth=0b00`
247 states that, again, the behaviour is not to be modified.
249 Only when elwidth is nonzero is the element width overridden to the
250 explicitly required value.
252 ## Elwidth for Integers:
254 | Value | Mnemonic | Description |
255 |-------|----------------|------------------------------------|
256 | 00 | DEFAULT | default behaviour for operation |
257 | 01 | `ELWIDTH=w` | Word: 32-bit integer |
258 | 10 | `ELWIDTH=h` | Halfword: 16-bit integer |
259 | 11 | `ELWIDTH=b` | Byte: 8-bit integer |
261 This encoding is chosen such that the byte width may be computed as
264 ## Elwidth for FP Registers:
266 | Value | Mnemonic | Description |
267 |-------|----------------|------------------------------------|
268 | 00 | DEFAULT | default behaviour for FP operation |
269 | 01 | `ELWIDTH=f32` | 32-bit IEEE 754 Single floating-point |
270 | 10 | `ELWIDTH=f16` | 16-bit IEEE 754 Half floating-point |
271 | 11 | `ELWIDTH=bf16` | Reserved for `bf16` |
274 [`bf16`](https://en.wikipedia.org/wiki/Bfloat16_floating-point_format)
275 is reserved for a future implementation of SV
277 Note that any IEEE754 FP operation in Power ISA ending in "s" (`fadds`) shall
278 perform its operation at **half** the ELWIDTH then padded back out
279 to ELWIDTH. `sv.fadds/ew=f32` shall perform an IEEE754 FP16 operation that is then "padded" to fill out to an IEEE754 FP32. When ELWIDTH=DEFAULT
280 clearly the behaviour of `sv.fadds` is performed at 32-bit accuracy
281 then padded back out to fit in IEEE754 FP64, exactly as for Scalar
282 v3.0B "single" FP. Any FP operation ending in "s" where ELWIDTH=f16
283 or ELWIDTH=bf16 is reserved and must raise an illegal instruction
284 (IEEE754 FP8 or BF8 are not defined).
288 Element-width overrides for CR Fields has no meaning. The bits
289 are therefore used for other purposes, or when Rc=1, the Elwidth
290 applies to the result being tested, but not to the Vector of CR Fields.
294 the default for SUBVL is 1 and its encoding is 0b00 to indicate that
295 SUBVL is effectively disabled (a SUBVL for-loop of only one element). this
296 lines up in combination with all other "default is all zeros" behaviour.
298 | Value | Mnemonic | Subvec | Description |
299 |-------|-----------|---------|------------------------|
300 | 00 | `SUBVL=1` | single | Sub-vector length of 1 |
301 | 01 | `SUBVL=2` | vec2 | Sub-vector length of 2 |
302 | 10 | `SUBVL=3` | vec3 | Sub-vector length of 3 |
303 | 11 | `SUBVL=4` | vec4 | Sub-vector length of 4 |
305 The SUBVL encoding value may be thought of as an inclusive range of a
306 sub-vector. SUBVL=2 represents a vec2, its encoding is 0b01, therefore
307 this may be considered to be elements 0b00 to 0b01 inclusive.
309 # MASK/MASK_SRC & MASKMODE Encoding
311 TODO: rename MASK_KIND to MASKMODE
313 One bit (`MASKMODE`) indicates the mode: CR or Int predication. The two
314 types may not be mixed.
316 Special note: to disable predication this field must
317 be set to zero in combination with Integer Predication also being set
318 to 0b000. this has the effect of enabling "all 1s" in the predicate
319 mask, which is equivalent to "not having any predication at all"
320 and consequently, in combination with all other default zeros, fully
321 disables SV (`scalar identity behaviour`).
323 `MASKMODE` may be set to one of 2 values:
325 | Value | Description |
326 |-----------|------------------------------------------------------|
327 | 0 | MASK/MASK_SRC are encoded using Integer Predication |
328 | 1 | MASK/MASK_SRC are encoded using CR-based Predication |
330 Integer Twin predication has a second set of 3 bits that uses the same
331 encoding thus allowing either the same register (r3, r10 or r31) to be used
332 for both src and dest, or different regs (one for src, one for dest).
334 Likewise CR based twin predication has a second set of 3 bits, allowing
335 a different test to be applied.
337 Note that it is assumed that Predicate Masks (whether INT or CR)
338 are read *before* the operations proceed. In practice (for CR Fields)
339 this creates an unnecessary block on parallelism. Therefore,
340 it is up to the programmer to ensure that the CR fields used as
341 Predicate Masks are not being written to by any parallel Vector Loop.
342 Doing so results in **UNDEFINED** behaviour, according to the definition
343 outlined in the Power ISA v3.0B Specification.
345 Hardware Implementations are therefore free and clear to delay reading
346 of individual CR fields until the actual predicated element operation
347 needs to take place, safe in the knowledge that no programmer will
348 have issued a Vector Instruction where previous elements could have
349 overwritten (destroyed) not-yet-executed CR-Predicated element operations.
351 ## Integer Predication (MASKMODE=0)
353 When the predicate mode bit is zero the 3 bits are interpreted as below.
354 Twin predication has an identical 3 bit field similarly encoded.
356 `MASK` and `MASK_SRC` may be set to one of 8 values, to provide the following meaning:
358 | Value | Mnemonic | Element `i` enabled if: |
359 |-------|----------|------------------------------|
360 | 000 | ALWAYS | predicate effectively all 1s |
361 | 001 | 1 << R3 | `i == R3` |
362 | 010 | R3 | `R3 & (1 << i)` is non-zero |
363 | 011 | ~R3 | `R3 & (1 << i)` is zero |
364 | 100 | R10 | `R10 & (1 << i)` is non-zero |
365 | 101 | ~R10 | `R10 & (1 << i)` is zero |
366 | 110 | R30 | `R30 & (1 << i)` is non-zero |
367 | 111 | ~R30 | `R30 & (1 << i)` is zero |
369 r10 and r30 are at the high end of temporary and unused registers, so as not to interfere with register allocation from ABIs.
371 ## CR-based Predication (MASKMODE=1)
373 When the predicate mode bit is one the 3 bits are interpreted as below.
374 Twin predication has an identical 3 bit field similarly encoded.
376 `MASK` and `MASK_SRC` may be set to one of 8 values, to provide the following meaning:
378 | Value | Mnemonic | Element `i` is enabled if |
379 |-------|----------|--------------------------|
380 | 000 | lt | `CR[offs+i].LT` is set |
381 | 001 | nl/ge | `CR[offs+i].LT` is clear |
382 | 010 | gt | `CR[offs+i].GT` is set |
383 | 011 | ng/le | `CR[offs+i].GT` is clear |
384 | 100 | eq | `CR[offs+i].EQ` is set |
385 | 101 | ne | `CR[offs+i].EQ` is clear |
386 | 110 | so/un | `CR[offs+i].FU` is set |
387 | 111 | ns/nu | `CR[offs+i].FU` is clear |
389 CR based predication. TODO: select alternate CR for twin predication? see
390 [[discussion]] Overlap of the two CR based predicates must be taken
391 into account, so the starting point for one of them must be suitably
392 high, or accept that for twin predication VL must not exceed the range
393 where overlap will occur, *or* that they use the same starting point
394 but select different *bits* of the same CRs
396 `offs` is defined as CR32 (4x8) so as to mesh cleanly with Vectorised Rc=1 operations (see below). Rc=1 operations start from CR8 (TBD).
398 The CR Predicates chosen must start on a boundary that Vectorised
399 CR operations can access cleanly, in full.
400 With EXTRA2 restricting starting points
401 to multiples of 8 (CR0, CR8, CR16...) both Vectorised Rc=1 and CR Predicate
402 Masks have to be adapted to fit on these boundaries as well.
404 # Extra Remapped Encoding <a name="extra_remap"> </a>
406 Shows all instruction-specific fields in the Remapped Encoding `RM[10:18]` for all instruction variants. Note that due to the very tight space, the encoding mode is *not* included in the prefix itself. The mode is "applied", similar to Power ISA "Forms" (X-Form, D-Form) on a per-instruction basis, and, like "Forms" are given a designation (below) of the form `RM-nP-nSnD`. The full list of which instructions use which remaps is here [[opcode_regs_deduped]]. (*Machine-readable CSV files have been provided which will make the task of creating SV-aware ISA decoders easier*).
408 These mappings are part of the SVP64 Specification in exactly the same
409 way as X-Form, D-Form. New Scalar instructions added to the Power ISA
410 will need a corresponding SVP64 Mapping, which can be derived by-rote
411 from examining the Register "Profile" of the instruction.
413 There are two categories: Single and Twin Predication.
414 Due to space considerations further subdivision of Single Predication
415 is based on whether the number of src operands is 2 or 3. With only
416 9 bits available some compromises have to be made.
418 * `RM-1P-3S1D` Single Predication dest/src1/2/3, applies to 4-operand instructions (fmadd, isel, madd).
419 * `RM-1P-2S1D` Single Predication dest/src1/2 applies to 3-operand instructions (src1 src2 dest)
420 * `RM-2P-1S1D` Twin Predication (src=1, dest=1)
421 * `RM-2P-1S1D-PU` Twin Predication (src=1, dest=1) with Pack/Unpack,
422 primarily for LDST (Immediate)' mv and swizzle mv
423 * `RM-2P-2S1D` Twin Predication (src=2, dest=1) primarily for LDST (Indexed)
424 * `RM-2P-1S2D` Twin Predication (src=1, dest=2) primarily for LDST Update
428 | Field Name | Field bits | Description |
429 |------------|------------|----------------------------------------|
430 | Rdest\_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
431 | Rsrc1\_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
432 | Rsrc2\_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
433 | Rsrc3\_EXTRA2 | `16:17` | extends Rsrc3 (R\*\_EXTRA2 Encoding) |
434 | EXTRA2_MODE | `18` | used by `divmod2du` and `maddedu` for RS |
436 These are for 3 operand in and either 1 or 2 out instructions.
437 3-in 1-out includes `madd RT,RA,RB,RC`. (DRAFT) instructions
438 such as `maddedu` have an implicit second destination, RS, the
439 selection of which is determined by bit 18.
443 | Field Name | Field bits | Description |
444 |------------|------------|-------------------------------------------|
445 | Rdest\_EXTRA3 | `10:12` | extends Rdest |
446 | Rsrc1\_EXTRA3 | `13:15` | extends Rsrc1 |
447 | Rsrc2\_EXTRA3 | `16:18` | extends Rsrc3 |
449 These are for 2 operand 1 dest instructions, such as `add RT, RA,
450 RB`. However also included are unusual instructions with an implicit dest
451 that is identical to its src reg, such as `rlwinmi`.
453 Normally, with instructions such as `rlwinmi`, the scalar v3.0B ISA would not have sufficient bit fields to allow
454 an alternative destination. With SV however this becomes possible.
455 Therefore, the fact that the dest is implicitly also a src should not
456 mislead: due to the *prefix* they are different SV regs.
458 * `rlwimi RA, RS, ...`
459 * Rsrc1_EXTRA3 applies to RS as the first src
460 * Rsrc2_EXTRA3 applies to RA as the secomd src
461 * Rdest_EXTRA3 applies to RA to create an **independent** dest.
463 With the addition of the EXTRA bits, the three registers
464 each may be *independently* made vector or scalar, and be independently
465 augmented to 7 bits in length.
469 | Field Name | Field bits | Description |
470 |------------|------------|----------------------------|
471 | Rdest_EXTRA3 | `10:12` | extends Rdest |
472 | Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 |
473 | MASK_SRC | `16:18` | Execution Mask for Source |
475 `RM-2P-2S` is for `stw` etc. and is Rsrc1 Rsrc2.
479 single-predicate, three registers (2 read, 1 write)
481 | Field Name | Field bits | Description |
482 |------------|------------|----------------------------|
483 | Rdest_EXTRA3 | `10:12` | extends Rdest |
484 | Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 |
485 | Rsrc2_EXTRA3 | `16:18` | extends Rsrc2 |
487 ## RM-2P-2S1D/1S2D/3S
489 The primary purpose for this encoding is for Twin Predication on LOAD
490 and STORE operations. see [[sv/ldst]] for detailed anslysis.
494 | Field Name | Field bits | Description |
495 |------------|------------|----------------------------|
496 | Rdest_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) |
497 | Rsrc1_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) |
498 | Rsrc2_EXTRA2 | `14:15` | extends Rsrc2 (R\*\_EXTRA2 Encoding) |
499 | MASK_SRC | `16:18` | Execution Mask for Source |
501 Note that for 1S2P the EXTRA2 dest and src names are switched (Rsrc_EXTRA2
502 is in bits 10:11, Rdest1_EXTRA2 in 12:13)
504 Also that for 3S (to cover `stdx` etc.) the names are switched to 3 src: Rsrc1_EXTRA2, Rsrc2_EXTRA2, Rsrc3_EXTRA2.
506 Note also that LD with update indexed, which takes 2 src and 2 dest
507 (e.g. `lhaux RT,RA,RB`), does not have room for 4 registers and also
508 Twin Predication. therefore these are treated as RM-2P-2S1D and the
509 src spec for RA is also used for the same RA as a dest.
511 Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing.
515 EXTRA is the means by which two things are achieved:
517 1. Registers are marked as either Vector *or Scalar*
518 2. Register field numbers (limited typically to 5 bit)
519 are extended in range, both for Scalar and Vector.
521 The register files are therefore extended:
523 * INT is extended from r0-31 to r0-127
524 * FP is extended from fp0-32 to fp0-fp127
525 * CR Fields are extended from CR0-7 to CR0-127
527 However due to pressure in `RM.EXTRA` not all these registers
528 are accessible by all instructions, particularly those with
529 a large number of operands (`madd`, `isel`).
531 In the following tables register numbers are constructed from the
532 standard v3.0B / v3.1B 32 bit register field (RA, FRA) and the EXTRA2
533 or EXTRA3 field from the SV Prefix, determined by the specific
534 RM-xx-yyyy designation for a given instruction.
535 The prefixing is arranged so that
536 interoperability between prefixing and nonprefixing of scalar registers
537 is direct and convenient (when the EXTRA field is all zeros).
539 A pseudocode algorithm explains the relationship, for INT/FP (see [[svp64/appendix]] for CRs)
544 spec = EXTRA2 << 1 # same as EXTRA3, shifted
546 return (RA << 2) | spec[1:2]
548 return (spec[1:2] << 5) | RA
550 Future versions may extend to 256 by shifting Vector numbering up.
551 Scalar will not be altered.
553 Note that in some cases the range of starting points for Vectors
558 If EXTRA3 is zero, maps to
559 "scalar identity" (scalar Power ISA field naming).
561 Fields are as follows:
564 * Mode: register is tagged as scalar or vector
565 * Range/Inc: the range of registers accessible from this EXTRA
566 encoding, and the "increment" (accessibility). "/4" means
567 that this EXTRA encoding may only give access (starting point)
569 * MSB..LSB: the bit field showing how the register opcode field
570 combines with EXTRA to give (extend) the register number (GPR)
572 | Value | Mode | Range/Inc | 6..0 |
573 |-----------|-------|---------------|---------------------|
574 | 000 | Scalar | `r0-r31`/1 | `0b00 RA` |
575 | 001 | Scalar | `r32-r63`/1 | `0b01 RA` |
576 | 010 | Scalar | `r64-r95`/1 | `0b10 RA` |
577 | 011 | Scalar | `r96-r127`/1 | `0b11 RA` |
578 | 100 | Vector | `r0-r124`/4 | `RA 0b00` |
579 | 101 | Vector | `r1-r125`/4 | `RA 0b01` |
580 | 110 | Vector | `r2-r126`/4 | `RA 0b10` |
581 | 111 | Vector | `r3-r127`/4 | `RA 0b11` |
585 If EXTRA2 is zero will map to
586 "scalar identity behaviour" i.e Scalar Power ISA register naming:
588 | Value | Mode | Range/inc | 6..0 |
589 |-----------|-------|---------------|-----------|
590 | 00 | Scalar | `r0-r31`/1 | `0b00 RA` |
591 | 01 | Scalar | `r32-r63`/1 | `0b01 RA` |
592 | 10 | Vector | `r0-r124`/4 | `RA 0b00` |
593 | 11 | Vector | `r2-r126`/4 | `RA 0b10` |
595 **Note that unlike in EXTRA3, in EXTRA2**:
597 * the GPR Vectors may only start from
598 `r0, r2, r4, r6, r8` and likewise FPR Vectors.
599 * the GPR Scalars may only go from `r0, r1, r2.. r63` and likewise FPR Scalars.
601 as there is insufficient bits to cover the full range.
605 CR Field encoding is essentially the same but made more complex due to CRs being bit-based. See [[svp64/appendix]] for explanation and pseudocode.
606 Note that Vectors may only start from `CR0, CR4, CR8, CR12, CR16, CR20`...
607 and Scalars may only go from `CR0, CR1, ... CR31`
609 Encoding shown MSB down to LSB
611 For a 5-bit operand (BA, BB, BT):
613 | Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
614 |-------|------|---------------|-----------| --------|---------|
615 | 000 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[4:2] | BA[1:0] |
616 | 001 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[4:2] | BA[1:0] |
617 | 010 | Scalar | `CR16-CR23`/1 | 0b0010 | BA[4:2] | BA[1:0] |
618 | 011 | Scalar | `CR24-CR31`/1 | 0b0011 | BA[4:2] | BA[1:0] |
619 | 100 | Vector | `CR0-CR112`/16 | BA[4:2] 0 | 0b000 | BA[1:0] |
620 | 101 | Vector | `CR4-CR116`/16 | BA[4:2] 0 | 0b100 | BA[1:0] |
621 | 110 | Vector | `CR8-CR120`/16 | BA[4:2] 1 | 0b000 | BA[1:0] |
622 | 111 | Vector | `CR12-CR124`/16 | BA[4:2] 1 | 0b100 | BA[1:0] |
624 For a 3-bit operand (e.g. BFA):
626 | Value | Mode | Range/Inc | 6..3 | 2..0 |
627 |-------|------|---------------|-----------| --------|
628 | 000 | Scalar | `CR0-CR7`/1 | 0b0000 | BFA |
629 | 001 | Scalar | `CR8-CR15`/1 | 0b0001 | BFA |
630 | 010 | Scalar | `CR16-CR23`/1 | 0b0010 | BFA |
631 | 011 | Scalar | `CR24-CR31`/1 | 0b0011 | BFA |
632 | 100 | Vector | `CR0-CR112`/16 | BFA 0 | 0b000 |
633 | 101 | Vector | `CR4-CR116`/16 | BFA 0 | 0b100 |
634 | 110 | Vector | `CR8-CR120`/16 | BFA 1 | 0b000 |
635 | 111 | Vector | `CR12-CR124`/16 | BFA 1 | 0b100 |
639 CR encoding is essentially the same but made more complex due to CRs being bit-based. See separate section for explanation and pseudocode.
640 Note that Vectors may only start from CR0, CR8, CR16, CR24, CR32...
643 Encoding shown MSB down to LSB
645 For a 5-bit operand (BA, BB, BC):
647 | Value | Mode | Range/Inc | 8..5 | 4..2 | 1..0 |
648 |-------|--------|----------------|---------|---------|---------|
649 | 00 | Scalar | `CR0-CR7`/1 | 0b0000 | BA[4:2] | BA[1:0] |
650 | 01 | Scalar | `CR8-CR15`/1 | 0b0001 | BA[4:2] | BA[1:0] |
651 | 10 | Vector | `CR0-CR112`/16 | BA[4:2] 0 | 0b000 | BA[1:0] |
652 | 11 | Vector | `CR8-CR120`/16 | BA[4:2] 1 | 0b000 | BA[1:0] |
654 For a 3-bit operand (e.g. BFA):
656 | Value | Mode | Range/Inc | 6..3 | 2..0 |
657 |-------|------|---------------|-----------| --------|
658 | 00 | Scalar | `CR0-CR7`/1 | 0b0000 | BFA |
659 | 01 | Scalar | `CR8-CR15`/1 | 0b0001 | BFA |
660 | 10 | Vector | `CR0-CR112`/16 | BFA 0 | 0b000 |
661 | 11 | Vector | `CR8-CR120`/16 | BFA 1 | 0b000 |
665 Now at its own page: [[svp64/appendix]]