1 """ Example 5: Making use of PyRTL and Introspection. """
3 from copy
import deepcopy
5 from migen
.fhdl
import verilog
8 # The following example shows how pyrtl can be used to make some interesting
9 # hardware structures using python introspection. In particular, this example
10 # makes a N-stage pipeline structure. Any specific pipeline is then a derived
11 # class of SimplePipeline where methods with names starting with "stage" are
12 # stages, and new members with names not starting with "_" are to be registered
15 class SimplePipeline(object):
16 """ Pipeline builder with auto generation of pipeline registers. """
18 def __init__(self
, pipe
):
20 self
._pipeline
_register
_map
= {}
21 self
._current
_stage
_num
= 0
25 for method
in dir(self
):
26 if method
.startswith('stage'):
27 stage_list
.append(method
)
28 for stage
in sorted(stage_list
):
29 stage_method
= getattr(self
, stage
)
31 self
._current
_stage
_num
+= 1
33 def __getattr__(self
, name
):
35 return self
._pipeline
_register
_map
[self
._current
_stage
_num
][name
]
38 'error, no pipeline register "%s" defined for stage %d'
39 % (name
, self
._current
_stage
_num
))
41 def __setattr__(self
, name
, value
):
42 if name
.startswith('_'):
43 # do not do anything tricky with variables starting with '_'
44 object.__setattr
__(self
, name
, value
)
46 next_stage
= self
._current
_stage
_num
+ 1
47 pipereg_id
= str(self
._current
_stage
_num
) + 'to' + str(next_stage
)
48 rname
= 'pipereg_' + pipereg_id
+ '_' + name
49 new_pipereg
= Signal(len(value
), name_override
=rname
)
50 if next_stage
not in self
._pipeline
_register
_map
:
51 self
._pipeline
_register
_map
[next_stage
] = {}
52 self
._pipeline
_register
_map
[next_stage
][name
] = new_pipereg
53 self
._pipe
.sync
+= new_pipereg
.eq(value
)
56 class SimplePipelineExample(SimplePipeline
):
57 """ A very simple pipeline to show how registers are inferred. """
59 def __init__(self
, pipe
):
60 super(SimplePipelineExample
, self
).__init
__(pipe
)
61 self
._loopback
= Signal()
66 self
.n
= ~self
._loopback
78 self
._pipe
.sync
+= self
._loopback
.eq(self
.n
)
80 class PipeModule(Module
):
84 if __name__
== "__main__":
85 example
= PipeModule()
86 pipe
= SimplePipelineExample(example
)
87 print(verilog
.convert(example
,