Implement hartstatus field.
[riscv-isa-sim.git] / riscv / debug_module.h
1 // See LICENSE for license details.
2 #ifndef _RISCV_DEBUG_MODULE_H
3 #define _RISCV_DEBUG_MODULE_H
4
5 #include <set>
6
7 #include "devices.h"
8
9 class sim_t;
10
11 class debug_module_t : public abstract_device_t
12 {
13 public:
14 debug_module_t(sim_t *sim);
15
16 bool load(reg_t addr, size_t len, uint8_t* bytes);
17 bool store(reg_t addr, size_t len, const uint8_t* bytes);
18
19 void ram_write32(unsigned int index, uint32_t value);
20 uint32_t ram_read32(unsigned int index);
21
22 void set_interrupt(uint32_t hartid) {
23 interrupt.insert(hartid);
24 }
25 void clear_interrupt(uint32_t hartid) {
26 interrupt.erase(hartid);
27 }
28 bool get_interrupt(uint32_t hartid) const {
29 return interrupt.find(hartid) != interrupt.end();
30 }
31
32 void set_halt_notification(uint32_t hartid) {
33 halt_notification.insert(hartid);
34 }
35 void clear_halt_notification(uint32_t hartid) {
36 halt_notification.erase(hartid);
37 }
38 bool get_halt_notification(uint32_t hartid) const {
39 return halt_notification.find(hartid) != halt_notification.end();
40 }
41
42 // Debug Module Interface that the debugger (in our case through JTAG DTM)
43 // uses to access the DM.
44 // Return true for success, false for failure.
45 bool dmi_read(unsigned address, uint32_t *value);
46 bool dmi_write(unsigned address, uint32_t value);
47
48 private:
49 sim_t *sim;
50 // Track which interrupts from module to debugger are set.
51 std::set<uint32_t> interrupt;
52 // Track which halt notifications from debugger to module are set.
53 std::set<uint32_t> halt_notification;
54 char debug_ram[DEBUG_RAM_SIZE];
55
56 static const unsigned datacount = 8;
57 static const unsigned progsize = 8;
58
59 uint32_t dmcontrol;
60 uint32_t abstractcs;
61 uint32_t data[datacount];
62 uint32_t ibuf[progsize];
63 };
64
65 #endif