1 // See LICENSE for license details.
3 #ifndef _RISCV_DECODE_H
4 #define _RISCV_DECODE_H
6 #if (-1 != ~0) || ((-1 >> 1) != -1)
7 # error spike requires a two''s-complement c++ implementation
10 #ifdef WORDS_BIGENDIAN
11 # error spike requires a little-endian host
20 #include "softfloat_types.h"
21 #include "specialize.h"
24 typedef int64_t sreg_t
;
25 typedef uint64_t reg_t
;
30 const int SV_NXPR
= NXPR
*4;
31 const int SV_NFPR
= NFPR
*4;
33 const int NCSR
= 4096;
44 #define FSR_RD_SHIFT 5
45 #define FSR_RD (0x7 << FSR_RD_SHIFT)
53 #define FSR_AEXC_SHIFT 0
54 #define FSR_NVA (FPEXC_NV << FSR_AEXC_SHIFT)
55 #define FSR_OFA (FPEXC_OF << FSR_AEXC_SHIFT)
56 #define FSR_UFA (FPEXC_UF << FSR_AEXC_SHIFT)
57 #define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT)
58 #define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT)
59 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
61 #define insn_length(x) \
62 (((x) & 0x03) < 0x03 ? 2 : \
63 ((x) & 0x1f) < 0x1f ? 4 : \
64 ((x) & 0x3f) < 0x3f ? 6 : \
66 #define MAX_INSN_LENGTH 8
69 typedef uint64_t insn_bits_t
;
74 insn_t(insn_bits_t bits
) : b(bits
) {}
75 insn_bits_t
bits() { return b
; }
76 int length() { return insn_length(b
); }
77 int64_t i_imm() { return int64_t(b
) >> 20; }
78 int64_t shamt() { return x(20, 6); }
79 int64_t s_imm() { return x(7, 5) + (xs(25, 7) << 5); }
80 int64_t sb_imm() { return (x(8, 4) << 1) + (x(25,6) << 5) + (x(7,1) << 11) + (imm_sign() << 12); }
81 int64_t u_imm() { return int64_t(b
) >> 12 << 12; }
82 int64_t uj_imm() { return (x(21, 10) << 1) + (x(20, 1) << 11) + (x(12, 8) << 12) + (imm_sign() << 20); }
83 uint64_t rd() { return x(7, 5); }
84 uint64_t rs1() { return x(15, 5); }
85 uint64_t rs2() { return x(20, 5); }
86 uint64_t rs3() { return x(27, 5); }
87 uint64_t rm() { return x(12, 3); }
88 uint64_t csr() { return x(20, 12); }
90 int64_t rvc_imm() { return x(2, 5) + (xs(12, 1) << 5); }
91 int64_t rvc_zimm() { return x(2, 5) + (x(12, 1) << 5); }
92 int64_t rvc_addi4spn_imm() { return (x(6, 1) << 2) + (x(5, 1) << 3) + (x(11, 2) << 4) + (x(7, 4) << 6); }
93 int64_t rvc_addi16sp_imm() { return (x(6, 1) << 4) + (x(2, 1) << 5) + (x(5, 1) << 6) + (x(3, 2) << 7) + (xs(12, 1) << 9); }
94 int64_t rvc_lwsp_imm() { return (x(4, 3) << 2) + (x(12, 1) << 5) + (x(2, 2) << 6); }
95 int64_t rvc_ldsp_imm() { return (x(5, 2) << 3) + (x(12, 1) << 5) + (x(2, 3) << 6); }
96 int64_t rvc_swsp_imm() { return (x(9, 4) << 2) + (x(7, 2) << 6); }
97 int64_t rvc_sdsp_imm() { return (x(10, 3) << 3) + (x(7, 3) << 6); }
98 int64_t rvc_lw_imm() { return (x(6, 1) << 2) + (x(10, 3) << 3) + (x(5, 1) << 6); }
99 int64_t rvc_ld_imm() { return (x(10, 3) << 3) + (x(5, 2) << 6); }
100 int64_t rvc_j_imm() { return (x(3, 3) << 1) + (x(11, 1) << 4) + (x(2, 1) << 5) + (x(7, 1) << 6) + (x(6, 1) << 7) + (x(9, 2) << 8) + (x(8, 1) << 10) + (xs(12, 1) << 11); }
101 int64_t rvc_b_imm() { return (x(3, 2) << 1) + (x(10, 2) << 3) + (x(2, 1) << 5) + (x(5, 2) << 6) + (xs(12, 1) << 8); }
102 int64_t rvc_simm3() { return x(10, 3); }
103 uint64_t rvc_rd() { return rd(); }
104 uint64_t rvc_rs1() { return rd(); }
105 uint64_t rvc_rs2() { return x(2, 5); }
106 uint64_t rvc_rs1s() { return 8 + x(7, 3); }
107 uint64_t rvc_rs2s() { return 8 + x(2, 3); }
110 uint64_t x(int lo
, int len
) { return (b
>> lo
) & ((insn_bits_t(1) << len
)-1); }
111 uint64_t xs(int lo
, int len
) { return int64_t(b
) << (64-lo
-len
) >> (64-len
); }
112 uint64_t imm_sign() { return xs(63, 1); }
115 template <class T
, size_t N
, bool zero_reg
>
119 void write(size_t i
, T value
)
121 if (!zero_reg
|| i
!= 0)
124 const T
& operator [] (size_t i
) const
132 // helpful macros, etc
133 #define MMU (*p->get_mmu())
134 #define STATE (*p->get_state())
135 #define READ_REG(reg) STATE.XPR[reg]
136 #define READ_FREG(reg) STATE.FPR[reg]
137 #define RS1 READ_REG(insn.rs1())
138 #define RS2 READ_REG(insn.rs2())
139 #define WRITE_RD(value) WRITE_REG(insn.rd(), value)
141 #ifndef RISCV_ENABLE_COMMITLOG
142 # define WRITE_REG(reg, value) STATE.XPR.write(reg, value)
143 # define WRITE_FREG(reg, value) DO_WRITE_FREG(reg, freg(value))
145 # define WRITE_REG(reg, value) ({ \
146 reg_t wdata = (value); /* value may have side effects */ \
147 STATE.log_reg_write = (commit_log_reg_t){(reg) << 1, {wdata, 0}}; \
148 STATE.XPR.write(reg, wdata); \
150 # define WRITE_FREG(reg, value) ({ \
151 freg_t wdata = freg(value); /* value may have side effects */ \
152 STATE.log_reg_write = (commit_log_reg_t){((reg) << 1) | 1, wdata}; \
153 DO_WRITE_FREG(reg, wdata); \
158 #define WRITE_RVC_RS1S(value) WRITE_REG(insn.rvc_rs1s(), value)
159 #define WRITE_RVC_RS2S(value) WRITE_REG(insn.rvc_rs2s(), value)
160 #define WRITE_RVC_FRS2S(value) WRITE_FREG(insn.rvc_rs2s(), value)
161 #define RVC_RS1 READ_REG(insn.rvc_rs1())
162 #define RVC_RS2 READ_REG(insn.rvc_rs2())
163 #define RVC_RS1S READ_REG(insn.rvc_rs1s())
164 #define RVC_RS2S READ_REG(insn.rvc_rs2s())
165 #define RVC_FRS2 READ_FREG(insn.rvc_rs2())
166 #define RVC_FRS2S READ_FREG(insn.rvc_rs2s())
167 #define RVC_SP READ_REG(X_SP)
170 #define FRS1 READ_FREG(insn.rs1())
171 #define FRS2 READ_FREG(insn.rs2())
172 #define FRS3 READ_FREG(insn.rs3())
173 #define dirty_fp_state (STATE.mstatus |= MSTATUS_FS | (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD))
174 #define dirty_ext_state (STATE.mstatus |= MSTATUS_XS | (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD))
175 #define DO_WRITE_FREG(reg, value) (STATE.FPR.write(reg, value), dirty_fp_state)
176 #define WRITE_FRD(value) WRITE_FREG(insn.rd(), value)
178 #define SHAMT (insn.i_imm() & 0x3F)
179 #define BRANCH_TARGET (pc + insn.sb_imm())
180 #define JUMP_TARGET (pc + insn.uj_imm())
181 #define RM ({ int rm = insn.rm(); \
182 if(rm == 7) rm = STATE.frm; \
183 if(rm > 4) throw trap_illegal_instruction(0); \
186 #define get_field(reg, mask) (((reg) & (decltype(reg))(mask)) / ((mask) & ~((mask) << 1)))
187 #define set_field(reg, mask, val) (((reg) & ~(decltype(reg))(mask)) | (((decltype(reg))(val) * ((mask) & ~((mask) << 1))) & (decltype(reg))(mask)))
189 #define require(x) if (unlikely(!(x))) throw trap_illegal_instruction(0)
190 #define require_privilege(p) require(STATE.prv >= (p))
191 #define require_rv64 require(xlen == 64)
192 #define require_rv32 require(xlen == 32)
193 #define require_extension(s) require(p->supports_extension(s))
194 #define require_fp require((STATE.mstatus & MSTATUS_FS) != 0)
195 #define require_accelerator require((STATE.mstatus & MSTATUS_XS) != 0)
197 #define set_fp_exceptions ({ if (softfloat_exceptionFlags) { \
199 STATE.fflags |= softfloat_exceptionFlags; \
201 softfloat_exceptionFlags = 0; })
203 #define sext32(x) ((sreg_t)(int32_t)(x))
204 #define zext32(x) ((reg_t)(uint32_t)(x))
206 #define _sext_xlen(x) (((sreg_t)(x) << (64-xlen)) >> (64-xlen))
207 #define sext_xlen(x) (((sreg_t)(x) << (64-xlen)) >> (64-xlen))
209 #define _zext_xlen(x) (((reg_t)(x) << (64-xlen)) >> (64-xlen))
210 #define zext_xlen(x) (((reg_t)(x) << (64-xlen)) >> (64-xlen))
213 do { p->check_pc_alignment(x); \
214 npc = _sext_xlen(x); \
217 #ifndef SPIKE_SIMPLEV
218 #define set_pc _set_pc
221 #define set_pc_and_serialize(x) \
222 do { reg_t __npc = (x) & p->pc_alignment_mask(); \
223 npc = PC_SERIALIZE_AFTER; \
228 do { set_pc_and_serialize(npc); \
229 npc = PC_SERIALIZE_WFI; \
232 #define serialize() set_pc_and_serialize(npc)
234 /* Sentinel PC values to serialize simulator pipeline */
235 #define PC_SERIALIZE_BEFORE 3
236 #define PC_SERIALIZE_AFTER 5
237 #define PC_SERIALIZE_WFI 7
238 #define invalid_pc(pc) ((pc) & 1)
240 /* Convenience wrappers to simplify softfloat code sequences */
241 #define unboxF16(r) (isBoxedF16(r) ? (uint16_t)r.v[0] : defaultNaNF16UI)
242 #define isBoxedF16(r) (isBoxedF32(r) && ((uint16_t)((r.v[0] >> 16) + 1) == 0))
243 #define isBoxedF32(r) (isBoxedF64(r) && ((uint32_t)((r.v[0] >> 32) + 1) == 0))
244 #define unboxF32(r) (isBoxedF32(r) ? (uint32_t)r.v[0] : defaultNaNF32UI)
245 #define isBoxedF64(r) ((r.v[1] + 1) == 0)
246 #define unboxF64(r) (isBoxedF64(r) ? r.v[0] : defaultNaNF64UI)
247 typedef float128_t freg_t
;
248 inline float16_t
f16(uint16_t v
) { return { v
}; }
249 inline float32_t
f32(uint32_t v
) { return { v
}; }
250 inline float64_t
f64(uint64_t v
) { return { v
}; }
251 inline float16_t
f16(freg_t r
) { return f16(unboxF16(r
)); }
252 inline float32_t
f32(freg_t r
) { return f32(unboxF32(r
)); }
253 inline float64_t
f64(freg_t r
) { return f64(unboxF64(r
)); }
254 inline float128_t
f128(freg_t r
) { return r
; }
255 inline freg_t
freg(float16_t f
) { return { ((uint64_t)-1 << 16) | f
.v
, (uint64_t)-1 }; }
256 inline freg_t
freg(float32_t f
) { return { ((uint64_t)-1 << 32) | f
.v
, (uint64_t)-1 }; }
257 inline freg_t
freg(float64_t f
) { return { f
.v
, (uint64_t)-1 }; }
258 inline freg_t
freg(float128_t f
) { return f
; }
259 #define F32_SIGN ((uint32_t)1 << 31)
260 #define F64_SIGN ((uint64_t)1 << 63)
261 #define fsgnj32(a, b, n, x) \
262 f32((((float32_t)f32(a)).v & ~F32_SIGN) | ((((x) ? ((float32_t)f32(a)).v : (n) ? F32_SIGN : 0) ^ ((float32_t)f32(b)).v) & F32_SIGN))
263 #define fsgnj64(a, b, n, x) \
264 f64((((float64_t)f64(a)).v & ~F64_SIGN) | ((((x) ? ((float64_t)f64(a)).v : (n) ? F64_SIGN : 0) ^ ((float64_t)f64(b)).v) & F64_SIGN))
266 #define isNaNF128(x) isNaNF128UI(((float128_t)x).v[1], ((float128_t)x).v[0])
267 inline float128_t
defaultNaNF128()
270 nan
.v
[1] = defaultNaNF128UI64
;
271 nan
.v
[0] = defaultNaNF128UI0
;
274 inline freg_t
fsgnj128(freg_t a
, freg_t b
, bool n
, bool x
)
276 a
.v
[1] = (a
.v
[1] & ~F64_SIGN
) | (((x
? a
.v
[1] : n
? F64_SIGN
: 0) ^ b
.v
[1]) & F64_SIGN
);
279 inline freg_t
f128_negate(freg_t a
)
285 #define validate_csr(which, write) ({ \
286 if (!STATE.serialized) return PC_SERIALIZE_BEFORE; \
287 STATE.serialized = false; \
288 unsigned csr_priv = get_field((which), 0x300); \
289 unsigned csr_read_only = get_field((which), 0xC00) == 3; \
290 if (((write) && csr_read_only) || STATE.prv < csr_priv) \
291 throw trap_illegal_instruction(0); \
294 // Seems that 0x0 doesn't work.
295 #define DEBUG_START 0x100
296 #define DEBUG_END (0x1000 - 1)