riscv/decode.h

   1 #ifndef _RISCV_DECODE_H
   2 #define _RISCV_DECODE_H
   3
   4 #define __STDC_LIMIT_MACROS
   5 #include <stdint.h>
   6
   7 #include "config.h"
   8
   9 typedef int int128_t __attribute__((mode(TI)));
  10 typedef unsigned int uint128_t __attribute__((mode(TI)));
  11
  12 typedef int64_t sreg_t;
  13 typedef uint64_t reg_t;
  14 typedef uint64_t freg_t;
  15
  16 const int OPCODE_BITS = 7;
  17
  18 const int XPRID_BITS = 5;
  19 const int NXPR = 1 << XPRID_BITS;
  20
  21 const int FPR_BITS = 64;
  22 const int FPRID_BITS = 5;
  23 const int NFPR = 1 << FPRID_BITS;
  24
  25 const int IMM_BITS = 12;
  26 const int IMMLO_BITS = 7;
  27 const int TARGET_BITS = 25;
  28 const int FUNCT_BITS = 3;
  29 const int FUNCTR_BITS = 7;
  30 const int FFUNCT_BITS = 2;
  31 const int RM_BITS = 3;
  32 const int BIGIMM_BITS = 20;
  33 const int BRANCH_ALIGN_BITS = 1;
  34 const int JUMP_ALIGN_BITS = 1;
  35
  36 #define SR_ET    0x0000000000000001ULL
  37 #define SR_EF    0x0000000000000002ULL
  38 #define SR_EV    0x0000000000000004ULL
  39 #define SR_EC    0x0000000000000008ULL
  40 #define SR_PS    0x0000000000000010ULL
  41 #define SR_S     0x0000000000000020ULL
  42 #define SR_UX    0x0000000000000040ULL
  43 #define SR_SX    0x0000000000000080ULL
  44 #define SR_IM    0x000000000000FF00ULL
  45 #define SR_ZERO  ~(SR_ET|SR_EF|SR_EV|SR_EC|SR_PS|SR_S|SR_UX|SR_SX|SR_IM)
  46 #define SR_IM_SHIFT 8
  47 #define TIMER_IRQ 7
  48
  49 #define CAUSE_EXCCODE 0x000000FF
  50 #define CAUSE_IP      0x0000FF00
  51 #define CAUSE_EXCCODE_SHIFT 0
  52 #define CAUSE_IP_SHIFT      8
  53
  54 #define FP_RD_NE  0
  55 #define FP_RD_0   1
  56 #define FP_RD_DN  2
  57 #define FP_RD_UP  3
  58 #define FP_RD_NMM 4
  59
  60 #define FSR_RD_SHIFT 5
  61 #define FSR_RD   (0x7 << FSR_RD_SHIFT)
  62
  63 #define FPEXC_NX 0x01
  64 #define FPEXC_UF 0x02
  65 #define FPEXC_OF 0x04
  66 #define FPEXC_DZ 0x08
  67 #define FPEXC_NV 0x10
  68
  69 #define FSR_AEXC_SHIFT 0
  70 #define FSR_NVA  (FPEXC_NV << FSR_AEXC_SHIFT)
  71 #define FSR_OFA  (FPEXC_OF << FSR_AEXC_SHIFT)
  72 #define FSR_UFA  (FPEXC_UF << FSR_AEXC_SHIFT)
  73 #define FSR_DZA  (FPEXC_DZ << FSR_AEXC_SHIFT)
  74 #define FSR_NXA  (FPEXC_NX << FSR_AEXC_SHIFT)
  75 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
  76
  77 #define FSR_ZERO ~(FSR_RD | FSR_AEXC)
  78
  79 // note: bit fields are in little-endian order
  80 struct itype_t
  81 {
  82   unsigned opcode : OPCODE_BITS;
  83   unsigned funct : FUNCT_BITS;
  84   signed imm12 : IMM_BITS;
  85   unsigned rs1 : XPRID_BITS;
  86   unsigned rd : XPRID_BITS;
  87 };
  88
  89 struct btype_t
  90 {
  91   unsigned opcode : OPCODE_BITS;
  92   unsigned funct : FUNCT_BITS;
  93   unsigned immlo : IMMLO_BITS;
  94   unsigned rs2 : XPRID_BITS;
  95   unsigned rs1 : XPRID_BITS;
  96   signed immhi : IMM_BITS-IMMLO_BITS;
  97 };
  98
  99 struct jtype_t
 100 {
 101   unsigned jump_opcode : OPCODE_BITS;
 102   signed target : TARGET_BITS;
 103 };
 104
 105 struct rtype_t
 106 {
 107   unsigned opcode : OPCODE_BITS;
 108   unsigned funct : FUNCT_BITS;
 109   unsigned functr : FUNCTR_BITS;
 110   unsigned rs2 : XPRID_BITS;
 111   unsigned rs1 : XPRID_BITS;
 112   unsigned rd : XPRID_BITS;
 113 };
 114
 115 struct ltype_t
 116 {
 117   unsigned opcode : OPCODE_BITS;
 118   unsigned bigimm : BIGIMM_BITS;
 119   unsigned rd : XPRID_BITS;
 120 };
 121
 122 struct ftype_t
 123 {
 124   unsigned opcode : OPCODE_BITS;
 125   unsigned ffunct : FFUNCT_BITS;
 126   unsigned rm : RM_BITS;
 127   unsigned rs3 : FPRID_BITS;
 128   unsigned rs2 : FPRID_BITS;
 129   unsigned rs1 : FPRID_BITS;
 130   unsigned rd  : FPRID_BITS;
 131 };
 132
 133 union insn_t
 134 {
 135   itype_t itype;
 136   jtype_t jtype;
 137   rtype_t rtype;
 138   btype_t btype;
 139   ltype_t ltype;
 140   ftype_t ftype;
 141   uint32_t bits;
 142 };
 143
 144 #if 0
 145 #include <stdio.h>
 146 class trace_writeback
 147 {
 148 public:
 149   trace_writeback(reg_t* _rf, int _rd) : rf(_rf), rd(_rd) {}
 150
 151   reg_t operator = (reg_t rhs)
 152   {
 153     printf("R[%x] <= %llx\n",rd,(long long)rhs);
 154     rf[rd] = rhs;
 155     return rhs;
 156   }
 157
 158 private:
 159   reg_t* rf;
 160   int rd;
 161 };
 162
 163 #define do_writeback(rf,rd) trace_writeback(rf,rd)
 164 #else
 165 #define do_writeback(rf,rd) rf[rd]
 166 #endif
 167
 168 // helpful macros, etc
 169 #define RS1 XPR[insn.rtype.rs1]
 170 #define RS2 XPR[insn.rtype.rs2]
 171 #define RD do_writeback(XPR,insn.rtype.rd)
 172 #define RA do_writeback(XPR,1)
 173 #define FRS1 FPR[insn.ftype.rs1]
 174 #define FRS2 FPR[insn.ftype.rs2]
 175 #define FRS3 FPR[insn.ftype.rs3]
 176 #define FRD FPR[insn.ftype.rd]
 177 #define BIGIMM insn.ltype.bigimm
 178 #define SIMM insn.itype.imm12
 179 #define BIMM ((signed)insn.btype.immlo | (insn.btype.immhi << IMMLO_BITS))
 180 #define SHAMT (insn.itype.imm12 & 0x3F)
 181 #define SHAMTW (insn.itype.imm12 & 0x1F)
 182 #define TARGET insn.jtype.target
 183 #define BRANCH_TARGET (pc + (BIMM << BRANCH_ALIGN_BITS))
 184 #define JUMP_TARGET (pc + (TARGET << JUMP_ALIGN_BITS))
 185 #define RM ((insn.ftype.rm != 7) ? insn.ftype.rm : \
 186             ((fsr & FSR_RD) >> FSR_RD_SHIFT))
 187
 188 #define require_supervisor if(!(sr & SR_S)) throw trap_privileged_instruction
 189 #define xpr64 (xprlen == 64)
 190 #define require_xpr64 if(!xpr64) throw trap_illegal_instruction
 191 #define require_xpr32 if(xpr64) throw trap_illegal_instruction
 192 #define require_fp if(!(sr & SR_EF)) throw trap_fp_disabled
 193 #define require_vector if(!(sr & SR_EV)) throw trap_vector_disabled
 194 #define cmp_trunc(reg) (reg_t(reg) << (64-xprlen))
 195 #define set_fp_exceptions ({ set_fsr(fsr | \
 196                                (softfloat_exceptionFlags << FSR_AEXC_SHIFT)); \
 197                              softfloat_exceptionFlags = 0; })
 198
 199 #define require_rvc if(!(sr & SR_EC)) throw trap_illegal_instruction
 200
 201 #define sext32(x) ((sreg_t)(int32_t)(x))
 202 #define insn_length(x) (((x).bits & 0x3) < 0x3 ? 2 : 4)
 203 #define sext_xprlen(x) ((sreg_t(x) << (64-xprlen)) >> (64-xprlen))
 204
 205 // RVC stuff
 206
 207 #define INSN_IS_RVC(x) (((x) & 0x3) < 0x3)
 208
 209 #define CRD do_writeback(XPR,(insn.bits >> 5) & 0x1f)
 210 #define CRS1 XPR[(insn.bits >> 10) & 0x1f]
 211 #define CRS2 XPR[(insn.bits >> 5) & 0x1f]
 212 #define CIMM6 ((int32_t)((insn.bits >> 10) & 0x3f) << 26 >> 26)
 213 #define CIMM10 ((int32_t)((insn.bits >> 5) & 0x3ff) << 22 >> 22)
 214 #define CJUMP_TARGET (pc + (CIMM10 << JUMP_ALIGN_BITS))
 215
 216 // vector stuff
 217 #define VL vl
 218
 219 #define UT_RS1(idx) uts[idx]->XPR[insn.rtype.rs1]
 220 #define UT_RS2(idx) uts[idx]->XPR[insn.rtype.rs2]
 221 #define UT_RD(idx) do_writeback(uts[idx]->XPR,insn.rtype.rd)
 222 #define UT_RA(idx) do_writeback(uts[idx]->XPR,1)
 223 #define UT_FRS1(idx) uts[idx]->FPR[insn.ftype.rs1]
 224 #define UT_FRS2(idx) uts[idx]->FPR[insn.ftype.rs2]
 225 #define UT_FRS3(idx) uts[idx]->FPR[insn.ftype.rs3]
 226 #define UT_FRD(idx) uts[idx]->FPR[insn.ftype.rd]
 227 #define UT_RM(idx) ((insn.ftype.rm != 7) ? insn.ftype.rm : \
 228               ((uts[idx]->fsr & FSR_RD) >> FSR_RD_SHIFT))
 229
 230 #define UT_LOOP_START for (int i=0;i<VL; i++) {
 231 #define UT_LOOP_END }
 232 #define UT_LOOP_RS1 UT_RS1(i)
 233 #define UT_LOOP_RS2 UT_RS2(i)
 234 #define UT_LOOP_RD UT_RD(i)
 235 #define UT_LOOP_RA UT_RA(i)
 236 #define UT_LOOP_FRS1 UT_FRS1(i)
 237 #define UT_LOOP_FRS2 UT_FRS2(i)
 238 #define UT_LOOP_FRS3 UT_FRS3(i)
 239 #define UT_LOOP_FRD UT_FRD(i)
 240 #define UT_LOOP_RM UT_RM(i)
 241
 242 #define VEC_LOAD(dst, func, inc) \
 243   reg_t addr = RS1; \
 244   UT_LOOP_START \
 245     UT_LOOP_##dst = mmu.func(addr); \
 246     addr += inc; \
 247   UT_LOOP_END
 248
 249 #define VEC_STORE(src, func, inc) \
 250   reg_t addr = RS1; \
 251   UT_LOOP_START \
 252     mmu.func(addr, UT_LOOP_##src); \
 253     addr += inc; \
 254   UT_LOOP_END
 255
 256 enum vt_command_t
 257 {
 258   vt_command_stop,
 259 };
 260
 261 #endif