riscv/decode.h

   1 #ifndef _RISCV_DECODE_H
   2 #define _RISCV_DECODE_H
   3
   4 #define __STDC_LIMIT_MACROS
   5 #include <stdint.h>
   6
   7 #include "config.h"
   8
   9 #ifdef RISCV_ENABLE_64BIT
  10 # define support_64bit 1
  11 #else
  12 # define support_64bit 0
  13 #endif
  14
  15 #ifdef RISCV_ENABLE_FPU
  16 # define support_fp 1
  17 #else
  18 # define support_fp 0
  19 #endif
  20
  21
  22 typedef int int128_t __attribute__((mode(TI)));
  23 typedef unsigned int uint128_t __attribute__((mode(TI)));
  24
  25 typedef int64_t sreg_t;
  26 typedef uint64_t reg_t;
  27 typedef uint64_t freg_t;
  28
  29 const int OPCODE_BITS = 7;
  30 const int JTYPE_OPCODE_BITS = 5;
  31
  32 const int GPR_BITS = 8*sizeof(reg_t);
  33 const int GPRID_BITS = 5;
  34 const int NGPR = 1 << GPRID_BITS;
  35
  36 const int FPR_BITS = 64;
  37 const int FPRID_BITS = 5;
  38 const int NFPR = 1 << FPRID_BITS;
  39
  40 const int IMM_BITS = 12;
  41 const int TARGET_BITS = 27;
  42 const int SHAMT_BITS = 6;
  43 const int FUNCT_BITS = 3;
  44 const int FUNCTR_BITS = 7;
  45 const int FFUNCT_BITS = 5;
  46 const int BIGIMM_BITS = 20;
  47 const int BRANCH_ALIGN_BITS = 1;
  48 const int JUMP_ALIGN_BITS = 1;
  49
  50 #define SR_ET    0x0000000000000001ULL
  51 #define SR_PS    0x0000000000000004ULL
  52 #define SR_S     0x0000000000000008ULL
  53 #define SR_EF    0x0000000000000010ULL
  54 #define SR_UX    0x0000000000000020ULL
  55 #define SR_SX    0x0000000000000040ULL
  56 #define SR_IM    0x000000000000FF00ULL
  57 #define SR_ZERO  ~(SR_ET | SR_PS | SR_S | SR_EF | SR_UX | SR_SX | SR_IM)
  58 #define SR_IM_SHIFT 8
  59 #define TIMER_IRQ 7
  60
  61 #define FP_RD_NE  0
  62 #define FP_RD_0   1
  63 #define FP_RD_DN  2
  64 #define FP_RD_UP  3
  65 #define FSR_RD_SHIFT 5
  66 #define FSR_RD   (0x3 << FSR_RD_SHIFT)
  67
  68 #define FPEXC_NX 0x01
  69 #define FPEXC_UF 0x02
  70 #define FPEXC_OF 0x04
  71 #define FPEXC_DZ 0x02
  72 #define FPEXC_NV 0x10
  73
  74 #define FSR_AEXC_SHIFT 0
  75 #define FSR_NVA  (FPEXC_NV << FSR_AEXC_SHIFT)
  76 #define FSR_OFA  (FPEXC_OF << FSR_AEXC_SHIFT)
  77 #define FSR_UFA  (FPEXC_UF << FSR_AEXC_SHIFT)
  78 #define FSR_DZA  (FPEXC_DZ << FSR_AEXC_SHIFT)
  79 #define FSR_NXA  (FPEXC_NX << FSR_AEXC_SHIFT)
  80 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
  81
  82 #define FSR_ZERO ~(FSR_RD | FSR_AEXC)
  83
  84 // note: bit fields are in little-endian order
  85 struct itype_t
  86 {
  87   signed imm12 : IMM_BITS;
  88   unsigned funct : FUNCT_BITS;
  89   unsigned rs1 : GPRID_BITS;
  90   unsigned rdi : GPRID_BITS;
  91   unsigned opcode : OPCODE_BITS;
  92 };
  93
  94 struct jtype_t
  95 {
  96   unsigned target : TARGET_BITS;
  97   unsigned jump_opcode : JTYPE_OPCODE_BITS;
  98 };
  99
 100 struct rtype_t
 101 {
 102   unsigned rdr : GPRID_BITS;
 103   unsigned functr : FUNCTR_BITS;
 104   unsigned funct : FUNCT_BITS;
 105   unsigned rs1 : GPRID_BITS;
 106   unsigned rs2 : GPRID_BITS;
 107   unsigned opcode : OPCODE_BITS;
 108 };
 109
 110 struct btype_t
 111 {
 112   unsigned bigimm : BIGIMM_BITS;
 113   unsigned rdi : GPRID_BITS;
 114   unsigned opcode : OPCODE_BITS;
 115 };
 116
 117 struct ftype_t
 118 {
 119   unsigned rdr : FPRID_BITS;
 120   unsigned rs3 : FPRID_BITS;
 121   unsigned ffunct : FFUNCT_BITS;
 122   unsigned rs1 : FPRID_BITS;
 123   unsigned rs2 : FPRID_BITS;
 124   unsigned opcode : OPCODE_BITS;
 125 };
 126
 127 union insn_t
 128 {
 129   itype_t itype;
 130   jtype_t jtype;
 131   rtype_t rtype;
 132   btype_t btype;
 133   ftype_t ftype;
 134   uint32_t bits;
 135 };
 136
 137 #if 0
 138 #include <stdio.h>
 139 class trace_writeback
 140 {
 141 public:
 142   trace_writeback(reg_t* _rf, int _rd) : rf(_rf), rd(_rd) {}
 143
 144   reg_t operator = (reg_t rhs)
 145   {
 146     printf("R[%x] <= %llx\n",rd,(long long)rhs);
 147     rf[rd] = rhs;
 148     return rhs;
 149   }
 150
 151 private:
 152   reg_t* rf;
 153   int rd;
 154 };
 155
 156 #define do_writeback(rf,rd) trace_writeback(rf,rd)
 157 #else
 158 #define do_writeback(rf,rd) rf[rd]
 159 #endif
 160
 161 // helpful macros, etc
 162 #define RS1 R[insn.rtype.rs1]
 163 #define RS2 R[insn.rtype.rs2]
 164 #define RDR do_writeback(R,insn.rtype.rdr)
 165 #define RDI do_writeback(R,insn.itype.rdi)
 166 #define FRS1 FR[insn.ftype.rs1]
 167 #define FRS2 FR[insn.ftype.rs2]
 168 #define FRS3 FR[insn.ftype.rs3]
 169 #define FRDR FR[insn.ftype.rdr]
 170 #define FRDI FR[insn.itype.rdi]
 171 #define BIGIMM insn.btype.bigimm
 172 #define SIMM insn.itype.imm12
 173 #define SHAMT (insn.itype.imm12 & 0x3F)
 174 #define SHAMTW (insn.itype.imm12 & 0x1F)
 175 #define TARGET insn.jtype.target
 176 #define BRANCH_TARGET (npc + (SIMM << BRANCH_ALIGN_BITS))
 177 #define JUMP_TARGET ((npc & ~((1<<(TARGET_BITS+JUMP_ALIGN_BITS))-1)) + (TARGET << JUMP_ALIGN_BITS))
 178 #define RM ((insn.ftype.ffunct >> 1) & 3)
 179
 180 #define require_supervisor if(!(sr & SR_S)) throw trap_privileged_instruction
 181 #define require64 if(gprlen != 64) throw trap_illegal_instruction
 182 #define require_fp if(!(sr & SR_EF)) throw trap_fp_disabled
 183 #define cmp_trunc(reg) (reg_t(reg) << (64-gprlen))
 184 #define set_fp_exceptions ({ set_fsr(fsr | \
 185                                (softfloat_exceptionFlags << FSR_AEXC_SHIFT)); \
 186                              softfloat_exceptionFlags = 0; })
 187
 188 static inline sreg_t sext32(int32_t arg)
 189 {
 190   return arg;
 191 }
 192
 193 #endif