riscv/decode.h

   1 #ifndef _RISCV_DECODE_H
   2 #define _RISCV_DECODE_H
   3
   4 #define __STDC_LIMIT_MACROS
   5 #include <stdint.h>
   6 typedef int int128_t __attribute__((mode(TI)));
   7 typedef unsigned int uint128_t __attribute__((mode(TI)));
   8
   9 #define support_64bit 1
  10 typedef int64_t sreg_t;
  11 typedef uint64_t reg_t;
  12 typedef uint64_t freg_t;
  13
  14 const int OPCODE_BITS = 7;
  15 const int JTYPE_OPCODE_BITS = 5;
  16
  17 const int GPR_BITS = 8*sizeof(reg_t);
  18 const int GPRID_BITS = 5;
  19 const int NGPR = 1 << GPRID_BITS;
  20
  21 const int FPR_BITS = 64;
  22 const int FPRID_BITS = 5;
  23 const int NFPR = 1 << FPRID_BITS;
  24
  25 const int IMM_BITS = 12;
  26 const int TARGET_BITS = 27;
  27 const int SHAMT_BITS = 6;
  28 const int FUNCT_BITS = 3;
  29 const int FFUNCT_BITS = 5;
  30 const int BIGIMM_BITS = 20;
  31
  32 #define SR_ET    0x0000000000000001ULL
  33 #define SR_PS    0x0000000000000004ULL
  34 #define SR_S     0x0000000000000008ULL
  35 #define SR_EF    0x0000000000000010ULL
  36 #define SR_UX    0x0000000000000020ULL
  37 #define SR_KX    0x0000000000000040ULL
  38 #define SR_IM    0x000000000000FF00ULL
  39 #define SR_ZERO  ~(SR_ET | SR_PS | SR_S | SR_EF | SR_UX | SR_KX | SR_IM)
  40
  41 #define FP_RD_NE 0
  42 #define FP_RD_0  1
  43 #define FP_RD_UP 2
  44 #define FP_RD_DN 3
  45 #define FSR_RD_SHIFT 10
  46 #define FSR_RD   (0x3 << FSR_RD_SHIFT)
  47
  48 #define FPEXC_NV 0x10
  49 #define FPEXC_OF 0x08
  50 #define FPEXC_UF 0x04
  51 #define FPEXC_DZ 0x02
  52 #define FPEXC_NX 0x01
  53
  54 #define FSR_AEXC_SHIFT 5
  55 #define FSR_NVA  (FPEXC_NV << FSR_AEXC_SHIFT)
  56 #define FSR_OFA  (FPEXC_OF << FSR_AEXC_SHIFT)
  57 #define FSR_UFA  (FPEXC_UF << FSR_AEXC_SHIFT)
  58 #define FSR_DZA  (FPEXC_DZ << FSR_AEXC_SHIFT)
  59 #define FSR_NXA  (FPEXC_NX << FSR_AEXC_SHIFT)
  60 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
  61
  62 #define FSR_CEXC_SHIFT 0
  63 #define FSR_NVC  (FPEXC_NV << FSR_AEXC_SHIFT)
  64 #define FSR_OFC  (FPEXC_OF << FSR_AEXC_SHIFT)
  65 #define FSR_UFC  (FPEXC_UF << FSR_AEXC_SHIFT)
  66 #define FSR_DZC  (FPEXC_DZ << FSR_AEXC_SHIFT)
  67 #define FSR_NXC  (FPEXC_NX << FSR_AEXC_SHIFT)
  68 #define FSR_CEXC (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
  69
  70 #define FSR_ZERO ~(FSR_RD | FSR_AEXC | FSR_CEXC)
  71
  72 // note: bit fields are in little-endian order
  73 struct itype_t
  74 {
  75   unsigned imm : IMM_BITS;
  76   unsigned funct : FUNCT_BITS;
  77   unsigned rb : GPRID_BITS;
  78   unsigned ra : GPRID_BITS;
  79   unsigned opcode : OPCODE_BITS;
  80 };
  81
  82 struct jtype_t
  83 {
  84   unsigned target : TARGET_BITS;
  85   unsigned jump_opcode : JTYPE_OPCODE_BITS;
  86 };
  87
  88 struct rtype_t
  89 {
  90   unsigned rc : GPRID_BITS;
  91   unsigned shamt : SHAMT_BITS;
  92   unsigned unused : 1;
  93   unsigned funct : FUNCT_BITS;
  94   unsigned rb : GPRID_BITS;
  95   unsigned ra : GPRID_BITS;
  96   unsigned opcode : OPCODE_BITS;
  97 };
  98
  99 struct btype_t
 100 {
 101   unsigned bigimm : BIGIMM_BITS;
 102   unsigned rt : GPRID_BITS;
 103   unsigned opcode : OPCODE_BITS;
 104 };
 105
 106 struct ftype_t
 107 {
 108   unsigned rc : FPRID_BITS;
 109   unsigned rd : FPRID_BITS;
 110   unsigned ffunct : FFUNCT_BITS;
 111   unsigned rb : FPRID_BITS;
 112   unsigned ra : FPRID_BITS;
 113   unsigned opcode : OPCODE_BITS;
 114 };
 115
 116 union insn_t
 117 {
 118   itype_t itype;
 119   jtype_t jtype;
 120   rtype_t rtype;
 121   btype_t btype;
 122   ftype_t ftype;
 123   uint32_t bits;
 124 };
 125
 126 // helpful macros, etc
 127 #define RA R[insn.rtype.ra]
 128 #define RB R[insn.rtype.rb]
 129 #define RC R[insn.rtype.rc]
 130 #define FRA FR[insn.ftype.ra]
 131 #define FRB FR[insn.ftype.rb]
 132 #define FRC FR[insn.ftype.rc]
 133 #define FRD FR[insn.ftype.rd]
 134 #define BIGIMM insn.btype.bigimm
 135 #define IMM insn.itype.imm
 136 #define SIMM ((int32_t)((uint32_t)insn.itype.imm<<(32-IMM_BITS))>>(32-IMM_BITS))
 137 #define SHAMT insn.rtype.shamt
 138 #define TARGET insn.jtype.target
 139 #define BRANCH_TARGET (npc + (SIMM*sizeof(insn_t)))
 140 #define JUMP_TARGET ((npc & ~((1<<TARGET_BITS)*sizeof(insn_t)-1)) + TARGET*sizeof(insn_t))
 141
 142 #define require_supervisor if(!(sr & SR_S)) throw trap_privileged_instruction
 143 #define require64 if(gprlen != 64) throw trap_illegal_instruction
 144 #define require_fp if(!(sr & SR_EF)) throw trap_fp_disabled
 145 #define cmp_trunc(reg) (reg_t(reg) << (64-gprlen))
 146 #define set_fp_exceptions ({ set_fsr((fsr & ~FSR_CEXC) | \
 147                                 (float_exception_flags << FSR_AEXC_SHIFT) | \
 148                                 (float_exception_flags << FSR_CEXC_SHIFT)); \
 149                              float_exception_flags = 0; })
 150
 151 static inline sreg_t sext32(int32_t arg)
 152 {
 153   return arg;
 154 }
 155
 156 #endif