1 #ifndef _RISCV_DECODE_H
2 #define _RISCV_DECODE_H
4 #define __STDC_LIMIT_MACROS
9 #ifdef RISCV_ENABLE_64BIT
10 # define support_64bit 1
12 # define support_64bit 0
15 #ifdef RISCV_ENABLE_FPU
22 typedef int int128_t
__attribute__((mode(TI
)));
23 typedef unsigned int uint128_t
__attribute__((mode(TI
)));
25 typedef int64_t sreg_t
;
26 typedef uint64_t reg_t
;
27 typedef uint64_t freg_t
;
29 const int OPCODE_BITS
= 7;
31 const int GPR_BITS
= 8*sizeof(reg_t
);
32 const int GPRID_BITS
= 5;
33 const int NGPR
= 1 << GPRID_BITS
;
35 const int FPR_BITS
= 64;
36 const int FPRID_BITS
= 5;
37 const int NFPR
= 1 << FPRID_BITS
;
39 const int IMM_BITS
= 12;
40 const int IMMLO_BITS
= 5;
41 const int TARGET_BITS
= 25;
42 const int SHAMT_BITS
= 6;
43 const int FUNCT_BITS
= 3;
44 const int FUNCTR_BITS
= 7;
45 const int FFUNCT_BITS
= 5;
46 const int BIGIMM_BITS
= 20;
47 const int BRANCH_ALIGN_BITS
= 1;
48 const int JUMP_ALIGN_BITS
= 1;
50 #define SR_ET 0x0000000000000001ULL
51 #define SR_PS 0x0000000000000004ULL
52 #define SR_S 0x0000000000000008ULL
53 #define SR_EF 0x0000000000000010ULL
54 #define SR_UX 0x0000000000000020ULL
55 #define SR_SX 0x0000000000000040ULL
56 #define SR_IM 0x000000000000FF00ULL
57 #define SR_ZERO ~(SR_ET | SR_PS | SR_S | SR_EF | SR_UX | SR_SX | SR_IM)
65 #define FSR_RD_SHIFT 5
66 #define FSR_RD (0x3 << FSR_RD_SHIFT)
74 #define FSR_AEXC_SHIFT 0
75 #define FSR_NVA (FPEXC_NV << FSR_AEXC_SHIFT)
76 #define FSR_OFA (FPEXC_OF << FSR_AEXC_SHIFT)
77 #define FSR_UFA (FPEXC_UF << FSR_AEXC_SHIFT)
78 #define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT)
79 #define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT)
80 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
82 #define FSR_ZERO ~(FSR_RD | FSR_AEXC)
84 // note: bit fields are in little-endian order
87 unsigned rd
: GPRID_BITS
;
88 unsigned rs1
: GPRID_BITS
;
89 signed imm12
: IMM_BITS
;
90 unsigned funct
: FUNCT_BITS
;
91 unsigned opcode
: OPCODE_BITS
;
96 unsigned immlo
: IMMLO_BITS
;
97 unsigned rs1
: GPRID_BITS
;
98 unsigned rs2
: GPRID_BITS
;
99 signed immhi
: IMM_BITS
-IMMLO_BITS
;
100 unsigned funct
: FUNCT_BITS
;
101 unsigned opcode
: OPCODE_BITS
;
106 signed target
: TARGET_BITS
;
107 unsigned jump_opcode
: OPCODE_BITS
;
112 unsigned rd
: GPRID_BITS
;
113 unsigned rs1
: GPRID_BITS
;
114 unsigned rs2
: GPRID_BITS
;
115 unsigned functr
: FUNCTR_BITS
;
116 unsigned funct
: FUNCT_BITS
;
117 unsigned opcode
: OPCODE_BITS
;
122 unsigned rd
: GPRID_BITS
;
123 unsigned bigimm
: BIGIMM_BITS
;
124 unsigned opcode
: OPCODE_BITS
;
129 unsigned rd
: FPRID_BITS
;
130 unsigned rs1
: FPRID_BITS
;
131 unsigned rs2
: FPRID_BITS
;
132 unsigned rs3
: FPRID_BITS
;
133 unsigned ffunct
: FFUNCT_BITS
;
134 unsigned opcode
: OPCODE_BITS
;
150 class trace_writeback
153 trace_writeback(reg_t
* _rf
, int _rd
) : rf(_rf
), rd(_rd
) {}
155 reg_t
operator = (reg_t rhs
)
157 printf("R[%x] <= %llx\n",rd
,(long long)rhs
);
167 #define do_writeback(rf,rd) trace_writeback(rf,rd)
169 #define do_writeback(rf,rd) rf[rd]
172 // helpful macros, etc
173 #define RS1 R[insn.rtype.rs1]
174 #define RS2 R[insn.rtype.rs2]
175 #define RD do_writeback(R,insn.rtype.rd)
176 #define RA do_writeback(R,1)
177 #define FRS1 FR[insn.ftype.rs1]
178 #define FRS2 FR[insn.ftype.rs2]
179 #define FRS3 FR[insn.ftype.rs3]
180 #define FRD FR[insn.ftype.rd]
181 #define BIGIMM insn.ltype.bigimm
182 #define SIMM insn.itype.imm12
183 #define BIMM ((signed)insn.btype.immlo | (insn.btype.immhi << IMMLO_BITS))
184 #define SHAMT (insn.itype.imm12 & 0x3F)
185 #define SHAMTW (insn.itype.imm12 & 0x1F)
186 #define TARGET insn.jtype.target
187 #define BRANCH_TARGET (npc + (BIMM << BRANCH_ALIGN_BITS))
188 #define JUMP_TARGET (npc + (TARGET << JUMP_ALIGN_BITS))
189 #define RM ((insn.ftype.ffunct & 4) ? (insn.ftype.ffunct & 3) : \
190 ((fsr & FSR_RD) >> FSR_RD_SHIFT))
192 #define require_supervisor if(!(sr & SR_S)) throw trap_privileged_instruction
193 #define require64 if(gprlen != 64) throw trap_illegal_instruction
194 #define require_fp if(!(sr & SR_EF)) throw trap_fp_disabled
195 #define cmp_trunc(reg) (reg_t(reg) << (64-gprlen))
196 #define set_fp_exceptions ({ set_fsr(fsr | \
197 (softfloat_exceptionFlags << FSR_AEXC_SHIFT)); \
198 softfloat_exceptionFlags = 0; })
200 static inline sreg_t
sext32(int32_t arg
)