riscv/decode.h

   1 #ifndef _RISCV_DECODE_H
   2 #define _RISCV_DECODE_H
   3
   4 #define __STDC_LIMIT_MACROS
   5 #include <stdint.h>
   6
   7 #include "config.h"
   8
   9 typedef int int128_t __attribute__((mode(TI)));
  10 typedef unsigned int uint128_t __attribute__((mode(TI)));
  11
  12 typedef int64_t sreg_t;
  13 typedef uint64_t reg_t;
  14 typedef uint64_t freg_t;
  15
  16 const int OPCODE_BITS = 7;
  17
  18 const int XPRID_BITS = 5;
  19 const int NXPR = 1 << XPRID_BITS;
  20
  21 const int FPR_BITS = 64;
  22 const int FPRID_BITS = 5;
  23 const int NFPR = 1 << FPRID_BITS;
  24
  25 const int IMM_BITS = 12;
  26 const int IMMLO_BITS = 7;
  27 const int TARGET_BITS = 25;
  28 const int FUNCT_BITS = 3;
  29 const int FUNCTR_BITS = 7;
  30 const int FFUNCT_BITS = 5;
  31 const int BIGIMM_BITS = 20;
  32 const int BRANCH_ALIGN_BITS = 1;
  33 const int JUMP_ALIGN_BITS = 1;
  34
  35 #define SR_ET    0x0000000000000001ULL
  36 #define SR_PS    0x0000000000000004ULL
  37 #define SR_S     0x0000000000000008ULL
  38 #define SR_EF    0x0000000000000010ULL
  39 #define SR_UX    0x0000000000000020ULL
  40 #define SR_SX    0x0000000000000040ULL
  41 #define SR_IM    0x000000000000FF00ULL
  42 #define SR_ZERO  ~(SR_ET | SR_PS | SR_S | SR_EF | SR_UX | SR_SX | SR_IM)
  43 #define SR_IM_SHIFT 8
  44 #define TIMER_IRQ 7
  45
  46 #define FP_RD_NE  0
  47 #define FP_RD_0   1
  48 #define FP_RD_DN  2
  49 #define FP_RD_UP  3
  50 #define FSR_RD_SHIFT 5
  51 #define FSR_RD   (0x3 << FSR_RD_SHIFT)
  52
  53 #define FPEXC_NX 0x01
  54 #define FPEXC_UF 0x02
  55 #define FPEXC_OF 0x04
  56 #define FPEXC_DZ 0x02
  57 #define FPEXC_NV 0x10
  58
  59 #define FSR_AEXC_SHIFT 0
  60 #define FSR_NVA  (FPEXC_NV << FSR_AEXC_SHIFT)
  61 #define FSR_OFA  (FPEXC_OF << FSR_AEXC_SHIFT)
  62 #define FSR_UFA  (FPEXC_UF << FSR_AEXC_SHIFT)
  63 #define FSR_DZA  (FPEXC_DZ << FSR_AEXC_SHIFT)
  64 #define FSR_NXA  (FPEXC_NX << FSR_AEXC_SHIFT)
  65 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
  66
  67 #define FSR_ZERO ~(FSR_RD | FSR_AEXC)
  68
  69 // note: bit fields are in little-endian order
  70 struct itype_t
  71 {
  72   unsigned opcode : OPCODE_BITS;
  73   unsigned funct : FUNCT_BITS;
  74   signed imm12 : IMM_BITS;
  75   unsigned rs1 : XPRID_BITS;
  76   unsigned rd : XPRID_BITS;
  77 };
  78
  79 struct btype_t
  80 {
  81   unsigned opcode : OPCODE_BITS;
  82   unsigned funct : FUNCT_BITS;
  83   unsigned immlo : IMMLO_BITS;
  84   unsigned rs2 : XPRID_BITS;
  85   unsigned rs1 : XPRID_BITS;
  86   signed immhi : IMM_BITS-IMMLO_BITS;
  87 };
  88
  89 struct jtype_t
  90 {
  91   unsigned jump_opcode : OPCODE_BITS;
  92   signed target : TARGET_BITS;
  93 };
  94
  95 struct rtype_t
  96 {
  97   unsigned opcode : OPCODE_BITS;
  98   unsigned funct : FUNCT_BITS;
  99   unsigned functr : FUNCTR_BITS;
 100   unsigned rs2 : XPRID_BITS;
 101   unsigned rs1 : XPRID_BITS;
 102   unsigned rd : XPRID_BITS;
 103 };
 104
 105 struct ltype_t
 106 {
 107   unsigned opcode : OPCODE_BITS;
 108   unsigned bigimm : BIGIMM_BITS;
 109   unsigned rd : XPRID_BITS;
 110 };
 111
 112 struct ftype_t
 113 {
 114   unsigned opcode : OPCODE_BITS;
 115   unsigned ffunct : FFUNCT_BITS;
 116   unsigned rs3 : FPRID_BITS;
 117   unsigned rs2 : FPRID_BITS;
 118   unsigned rs1 : FPRID_BITS;
 119   unsigned rd  : FPRID_BITS;
 120 };
 121
 122 union insn_t
 123 {
 124   itype_t itype;
 125   jtype_t jtype;
 126   rtype_t rtype;
 127   btype_t btype;
 128   ltype_t ltype;
 129   ftype_t ftype;
 130   uint32_t bits;
 131 };
 132
 133 #if 0
 134 #include <stdio.h>
 135 class trace_writeback
 136 {
 137 public:
 138   trace_writeback(reg_t* _rf, int _rd) : rf(_rf), rd(_rd) {}
 139
 140   reg_t operator = (reg_t rhs)
 141   {
 142     printf("R[%x] <= %llx\n",rd,(long long)rhs);
 143     rf[rd] = rhs;
 144     return rhs;
 145   }
 146
 147 private:
 148   reg_t* rf;
 149   int rd;
 150 };
 151
 152 #define do_writeback(rf,rd) trace_writeback(rf,rd)
 153 #else
 154 #define do_writeback(rf,rd) rf[rd]
 155 #endif
 156
 157 // helpful macros, etc
 158 #define RS1 XPR[insn.rtype.rs1]
 159 #define RS2 XPR[insn.rtype.rs2]
 160 #define RD do_writeback(XPR,insn.rtype.rd)
 161 #define RA do_writeback(XPR,1)
 162 #define FRS1 FPR[insn.ftype.rs1]
 163 #define FRS2 FPR[insn.ftype.rs2]
 164 #define FRS3 FPR[insn.ftype.rs3]
 165 #define FRD FPR[insn.ftype.rd]
 166 #define BIGIMM insn.ltype.bigimm
 167 #define SIMM insn.itype.imm12
 168 #define BIMM ((signed)insn.btype.immlo | (insn.btype.immhi << IMMLO_BITS))
 169 #define SHAMT (insn.itype.imm12 & 0x3F)
 170 #define SHAMTW (insn.itype.imm12 & 0x1F)
 171 #define TARGET insn.jtype.target
 172 #define BRANCH_TARGET (npc + (BIMM << BRANCH_ALIGN_BITS))
 173 #define JUMP_TARGET (npc + (TARGET << JUMP_ALIGN_BITS))
 174 #define RM ((insn.ftype.ffunct & 4) ? (insn.ftype.ffunct & 3) : \
 175             ((fsr & FSR_RD) >> FSR_RD_SHIFT))
 176
 177 #define require_supervisor if(!(sr & SR_S)) throw trap_privileged_instruction
 178 #define xpr64 (xprlen == 64)
 179 #define require_xpr64 if(!xpr64) throw trap_illegal_instruction
 180 #define require_fp if(!(sr & SR_EF)) throw trap_fp_disabled
 181 #define cmp_trunc(reg) (reg_t(reg) << (64-xprlen))
 182 #define set_fp_exceptions ({ set_fsr(fsr | \
 183                                (softfloat_exceptionFlags << FSR_AEXC_SHIFT)); \
 184                              softfloat_exceptionFlags = 0; })
 185
 186 static inline sreg_t sext32(int32_t arg)
 187 {
 188   return arg;
 189 }
 190
 191 #define sext_xprlen(x) ((sreg_t(x) << (64-xprlen)) >> (64-xprlen))
 192
 193 #endif