riscv/decode.h

   1 #ifndef _RISCV_DECODE_H
   2 #define _RISCV_DECODE_H
   3
   4 #define __STDC_LIMIT_MACROS
   5 #include <stdint.h>
   6
   7 #include "config.h"
   8
   9 typedef int int128_t __attribute__((mode(TI)));
  10 typedef unsigned int uint128_t __attribute__((mode(TI)));
  11
  12 typedef int64_t sreg_t;
  13 typedef uint64_t reg_t;
  14 typedef uint64_t freg_t;
  15
  16 const int OPCODE_BITS = 7;
  17
  18 const int XPRID_BITS = 5;
  19 const int NXPR = 1 << XPRID_BITS;
  20
  21 const int FPR_BITS = 64;
  22 const int FPRID_BITS = 5;
  23 const int NFPR = 1 << FPRID_BITS;
  24
  25 const int IMM_BITS = 12;
  26 const int IMMLO_BITS = 7;
  27 const int TARGET_BITS = 25;
  28 const int FUNCT_BITS = 3;
  29 const int FUNCTR_BITS = 7;
  30 const int FFUNCT_BITS = 2;
  31 const int RM_BITS = 3;
  32 const int BIGIMM_BITS = 20;
  33 const int BRANCH_ALIGN_BITS = 1;
  34 const int JUMP_ALIGN_BITS = 1;
  35
  36 #define SR_ET    0x0000000000000001ULL
  37 #define SR_PS    0x0000000000000004ULL
  38 #define SR_S     0x0000000000000008ULL
  39 #define SR_EF    0x0000000000000010ULL
  40 #define SR_UX    0x0000000000000020ULL
  41 #define SR_SX    0x0000000000000040ULL
  42 #define SR_IM    0x000000000000FF00ULL
  43 #define SR_ZERO  ~(SR_ET | SR_PS | SR_S | SR_EF | SR_UX | SR_SX | SR_IM)
  44 #define SR_IM_SHIFT 8
  45 #define TIMER_IRQ 7
  46
  47 #define CAUSE_EXCCODE 0x000000FF
  48 #define CAUSE_IP      0x0000FF00
  49 #define CAUSE_EXCCODE_SHIFT 0
  50 #define CAUSE_IP_SHIFT      8
  51
  52 #define FP_RD_NE  0
  53 #define FP_RD_0   1
  54 #define FP_RD_DN  2
  55 #define FP_RD_UP  3
  56 #define FP_RD_NMM 4
  57
  58 #define FSR_RD_SHIFT 5
  59 #define FSR_RD   (0x7 << FSR_RD_SHIFT)
  60
  61 #define FPEXC_NX 0x01
  62 #define FPEXC_UF 0x02
  63 #define FPEXC_OF 0x04
  64 #define FPEXC_DZ 0x02
  65 #define FPEXC_NV 0x10
  66
  67 #define FSR_AEXC_SHIFT 0
  68 #define FSR_NVA  (FPEXC_NV << FSR_AEXC_SHIFT)
  69 #define FSR_OFA  (FPEXC_OF << FSR_AEXC_SHIFT)
  70 #define FSR_UFA  (FPEXC_UF << FSR_AEXC_SHIFT)
  71 #define FSR_DZA  (FPEXC_DZ << FSR_AEXC_SHIFT)
  72 #define FSR_NXA  (FPEXC_NX << FSR_AEXC_SHIFT)
  73 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
  74
  75 #define FSR_ZERO ~(FSR_RD | FSR_AEXC)
  76
  77 // note: bit fields are in little-endian order
  78 struct itype_t
  79 {
  80   unsigned opcode : OPCODE_BITS;
  81   unsigned funct : FUNCT_BITS;
  82   signed imm12 : IMM_BITS;
  83   unsigned rs1 : XPRID_BITS;
  84   unsigned rd : XPRID_BITS;
  85 };
  86
  87 struct btype_t
  88 {
  89   unsigned opcode : OPCODE_BITS;
  90   unsigned funct : FUNCT_BITS;
  91   unsigned immlo : IMMLO_BITS;
  92   unsigned rs2 : XPRID_BITS;
  93   unsigned rs1 : XPRID_BITS;
  94   signed immhi : IMM_BITS-IMMLO_BITS;
  95 };
  96
  97 struct jtype_t
  98 {
  99   unsigned jump_opcode : OPCODE_BITS;
 100   signed target : TARGET_BITS;
 101 };
 102
 103 struct rtype_t
 104 {
 105   unsigned opcode : OPCODE_BITS;
 106   unsigned funct : FUNCT_BITS;
 107   unsigned functr : FUNCTR_BITS;
 108   unsigned rs2 : XPRID_BITS;
 109   unsigned rs1 : XPRID_BITS;
 110   unsigned rd : XPRID_BITS;
 111 };
 112
 113 struct ltype_t
 114 {
 115   unsigned opcode : OPCODE_BITS;
 116   unsigned bigimm : BIGIMM_BITS;
 117   unsigned rd : XPRID_BITS;
 118 };
 119
 120 struct ftype_t
 121 {
 122   unsigned opcode : OPCODE_BITS;
 123   unsigned ffunct : FFUNCT_BITS;
 124   unsigned rm : RM_BITS;
 125   unsigned rs3 : FPRID_BITS;
 126   unsigned rs2 : FPRID_BITS;
 127   unsigned rs1 : FPRID_BITS;
 128   unsigned rd  : FPRID_BITS;
 129 };
 130
 131 union insn_t
 132 {
 133   itype_t itype;
 134   jtype_t jtype;
 135   rtype_t rtype;
 136   btype_t btype;
 137   ltype_t ltype;
 138   ftype_t ftype;
 139   uint32_t bits;
 140 };
 141
 142 #if 0
 143 #include <stdio.h>
 144 class trace_writeback
 145 {
 146 public:
 147   trace_writeback(reg_t* _rf, int _rd) : rf(_rf), rd(_rd) {}
 148
 149   reg_t operator = (reg_t rhs)
 150   {
 151     printf("R[%x] <= %llx\n",rd,(long long)rhs);
 152     rf[rd] = rhs;
 153     return rhs;
 154   }
 155
 156 private:
 157   reg_t* rf;
 158   int rd;
 159 };
 160
 161 #define do_writeback(rf,rd) trace_writeback(rf,rd)
 162 #else
 163 #define do_writeback(rf,rd) rf[rd]
 164 #endif
 165
 166 // helpful macros, etc
 167 #define RS1 XPR[insn.rtype.rs1]
 168 #define RS2 XPR[insn.rtype.rs2]
 169 #define RD do_writeback(XPR,insn.rtype.rd)
 170 #define RA do_writeback(XPR,1)
 171 #define FRS1 FPR[insn.ftype.rs1]
 172 #define FRS2 FPR[insn.ftype.rs2]
 173 #define FRS3 FPR[insn.ftype.rs3]
 174 #define FRD FPR[insn.ftype.rd]
 175 #define BIGIMM insn.ltype.bigimm
 176 #define SIMM insn.itype.imm12
 177 #define BIMM ((signed)insn.btype.immlo | (insn.btype.immhi << IMMLO_BITS))
 178 #define SHAMT (insn.itype.imm12 & 0x3F)
 179 #define SHAMTW (insn.itype.imm12 & 0x1F)
 180 #define TARGET insn.jtype.target
 181 #define BRANCH_TARGET (pc + (BIMM << BRANCH_ALIGN_BITS))
 182 #define JUMP_TARGET (pc + (TARGET << JUMP_ALIGN_BITS))
 183 #define RM ((insn.ftype.rm != 7) ? insn.ftype.rm : \
 184             ((fsr & FSR_RD) >> FSR_RD_SHIFT))
 185
 186 #define require_supervisor if(!(sr & SR_S)) throw trap_privileged_instruction
 187 #define xpr64 (xprlen == 64)
 188 #define require_xpr64 if(!xpr64) throw trap_illegal_instruction
 189 #define require_xpr32 if(xpr64) throw trap_illegal_instruction
 190 #define require_fp if(!(sr & SR_EF)) throw trap_fp_disabled
 191 #define cmp_trunc(reg) (reg_t(reg) << (64-xprlen))
 192 #define set_fp_exceptions ({ set_fsr(fsr | \
 193                                (softfloat_exceptionFlags << FSR_AEXC_SHIFT)); \
 194                              softfloat_exceptionFlags = 0; })
 195
 196 static inline sreg_t sext32(int32_t arg)
 197 {
 198   return arg;
 199 }
 200
 201 #define sext_xprlen(x) ((sreg_t(x) << (64-xprlen)) >> (64-xprlen))
 202
 203 #endif