1 // See LICENSE for license details.
3 #ifndef _RISCV_DECODE_H
4 #define _RISCV_DECODE_H
6 #if (-1 != ~0) || ((-1 >> 1) != -1)
7 # error spike requires a two''s-complement c++ implementation
10 #define __STDC_LIMIT_MACROS
18 typedef int int128_t
__attribute__((mode(TI
)));
19 typedef unsigned int uint128_t
__attribute__((mode(TI
)));
21 typedef int64_t sreg_t
;
22 typedef uint64_t reg_t
;
23 typedef uint64_t freg_t
;
34 #define FSR_RD_SHIFT 5
35 #define FSR_RD (0x7 << FSR_RD_SHIFT)
43 #define FSR_AEXC_SHIFT 0
44 #define FSR_NVA (FPEXC_NV << FSR_AEXC_SHIFT)
45 #define FSR_OFA (FPEXC_OF << FSR_AEXC_SHIFT)
46 #define FSR_UFA (FPEXC_UF << FSR_AEXC_SHIFT)
47 #define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT)
48 #define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT)
49 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
54 uint32_t bits() { return b
; }
55 int32_t i_imm() { return int32_t(b
) >> 20; }
56 int32_t s_imm() { return x(7, 5) + (xs(25, 7) << 5); }
57 int32_t sb_imm() { return (x(8, 4) << 1) + (x(25,6) << 5) + (x(7,1) << 11) + (imm_sign() << 12); }
58 int32_t u_imm() { return int32_t(b
) >> 12 << 12; }
59 int32_t uj_imm() { return (x(21, 10) << 1) + (x(20, 1) << 11) + (x(12, 8) << 12) + (imm_sign() << 20); }
60 uint32_t rd() { return x(7, 5); }
61 uint32_t rs1() { return x(15, 5); }
62 uint32_t rs2() { return x(20, 5); }
63 uint32_t rs3() { return x(27, 5); }
64 uint32_t rm() { return x(12, 3); }
65 uint32_t csr() { return x(20, 12); }
68 uint32_t x(int lo
, int len
) { return b
<< (32-lo
-len
) >> (32-len
); }
69 uint32_t xs(int lo
, int len
) { return int32_t(b
) << (32-lo
-len
) >> (32-len
); }
70 uint32_t imm_sign() { return xs(31, 1); }
73 template <class T
, size_t N
, bool zero_reg
>
79 memset(data
, 0, sizeof(data
));
81 void write(size_t i
, T value
)
83 if (!(zero_reg
&& i
== 0))
86 const T
& operator [] (size_t i
) const
94 // helpful macros, etc
95 #define MMU (*p->get_mmu())
96 #define RS1 p->get_state()->XPR[insn.rs1()]
97 #define RS2 p->get_state()->XPR[insn.rs2()]
98 #define WRITE_RD(value) p->get_state()->XPR.write(insn.rd(), value)
100 #ifdef RISCV_ENABLE_COMMITLOG
102 #define WRITE_RD(value) ({ \
103 bool in_spvr = p->get_state()->sr & SR_S; \
104 reg_t wdata = value; /* value is a func with side-effects */ \
106 fprintf(stderr, "x%u 0x%016" PRIx64, insn.rd(), ((uint64_t) wdata)); \
107 p->get_state()->XPR.write(insn.rd(), wdata); \
111 #define FRS1 p->get_state()->FPR[insn.rs1()]
112 #define FRS2 p->get_state()->FPR[insn.rs2()]
113 #define FRS3 p->get_state()->FPR[insn.rs3()]
114 #define WRITE_FRD(value) p->get_state()->FPR.write(insn.rd(), value)
116 #ifdef RISCV_ENABLE_COMMITLOG
118 #define WRITE_FRD(value) ({ \
119 bool in_spvr = p->get_state()->sr & SR_S; \
120 freg_t wdata = value; /* value is a func with side-effects */ \
122 fprintf(stderr, "f%u 0x%016" PRIx64, insn.rd(), ((uint64_t) wdata)); \
123 p->get_state()->FPR.write(insn.rd(), wdata); \
129 #define SHAMT (insn.i_imm() & 0x3F)
130 #define BRANCH_TARGET (pc + insn.sb_imm())
131 #define JUMP_TARGET (pc + insn.uj_imm())
132 #define RM ({ int rm = insn.rm(); \
133 if(rm == 7) rm = p->get_state()->frm; \
134 if(rm > 4) throw trap_illegal_instruction(); \
137 #define xpr64 (xprlen == 64)
139 #define require_supervisor if(unlikely(!(p->get_state()->sr & SR_S))) throw trap_privileged_instruction()
140 #define require_xpr64 if(unlikely(!xpr64)) throw trap_illegal_instruction()
141 #define require_xpr32 if(unlikely(xpr64)) throw trap_illegal_instruction()
142 #ifndef RISCV_ENABLE_FPU
143 # define require_fp throw trap_illegal_instruction()
145 # define require_fp if(unlikely(!(p->get_state()->sr & SR_EF))) throw trap_fp_disabled()
147 #define require_accelerator if(unlikely(!(p->get_state()->sr & SR_EA))) throw trap_accelerator_disabled()
149 #define cmp_trunc(reg) (reg_t(reg) << (64-xprlen))
150 #define set_fp_exceptions ({ p->get_state()->fflags |= softfloat_exceptionFlags; \
151 softfloat_exceptionFlags = 0; })
153 #define sext32(x) ((sreg_t)(int32_t)(x))
154 #define zext32(x) ((reg_t)(uint32_t)(x))
155 #define sext_xprlen(x) (((sreg_t)(x) << (64-xprlen)) >> (64-xprlen))
156 #define zext_xprlen(x) (((reg_t)(x) << (64-xprlen)) >> (64-xprlen))
158 #define insn_length(x) \
159 (((x) & 0x03) < 0x03 ? 2 : \
160 ((x) & 0x1f) < 0x1f ? 4 : \
161 ((x) & 0x3f) < 0x3f ? 6 : \
165 do { if ((x) & 3 /* For now... */) \
166 throw trap_instruction_address_misaligned(); \
170 #define validate_csr(which, write) ({ \
171 int write_priv = ((which) >> 10) & 3; \
172 int read_priv = ((which) >> 8) & 3; \
173 if (read_priv > 0 || (write_priv > 0 && (write))) require_supervisor; \