1 // See LICENSE for license details.
3 #ifndef _RISCV_DECODE_H
4 #define _RISCV_DECODE_H
6 #define __STDC_LIMIT_MACROS
13 typedef int int128_t
__attribute__((mode(TI
)));
14 typedef unsigned int uint128_t
__attribute__((mode(TI
)));
16 typedef int64_t sreg_t
;
17 typedef uint64_t reg_t
;
18 typedef uint64_t freg_t
;
29 #define FSR_RD_SHIFT 5
30 #define FSR_RD (0x7 << FSR_RD_SHIFT)
38 #define FSR_AEXC_SHIFT 0
39 #define FSR_NVA (FPEXC_NV << FSR_AEXC_SHIFT)
40 #define FSR_OFA (FPEXC_OF << FSR_AEXC_SHIFT)
41 #define FSR_UFA (FPEXC_UF << FSR_AEXC_SHIFT)
42 #define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT)
43 #define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT)
44 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
46 #define FSR_ZERO ~(FSR_RD | FSR_AEXC)
51 uint32_t bits() { return b
; }
52 reg_t
i_imm() { return x(11, 11) | (imm_sign() << 11); }
53 reg_t
s_imm() { return x(11, 6) | (x(27, 5) << 6) | (imm_sign() << 11); }
54 reg_t
sb_imm() { return (x(12, 5) << 1) | (x(27, 5) << 6) | (x(11, 1) << 11) | (imm_sign() << 12); }
55 reg_t
u_imm() { return (x(22, 5) << 12) | (x(7, 3) << 17) | (x(11, 11) << 20) | (imm_sign() << 31); }
56 reg_t
uj_imm() { return (x(12, 10) << 1) | (x(11, 1) << 11) | (x(22, 5) << 12) | (x(7, 3) << 17) | (imm_sign() << 20); }
57 uint32_t rd() { return x(27, 5); }
58 uint32_t rs1() { return x(22, 5); }
59 uint32_t rs2() { return x(17, 5); }
60 uint32_t rs3() { return x(12, 5); }
61 uint32_t rm() { return x(9, 3); }
64 reg_t
x(int lo
, int len
) { return b
<< (32-lo
-len
) >> (32-len
); }
65 reg_t
imm_sign() { return -x(10, 1); }
72 write_port_t(T
& _t
) : t(_t
) {}
73 T
& operator = (const T
& rhs
)
84 template <class T
, size_t N
, bool zero_reg
>
90 memset(data
, 0, sizeof(data
));
92 write_port_t
<T
> write_port(size_t i
)
95 const_cast<T
&>(data
[0]) = 0;
96 return write_port_t
<T
>(data
[i
]);
98 const T
& operator [] (size_t i
) const
101 const_cast<T
&>(data
[0]) = 0;
108 // helpful macros, etc
109 #define MMU (*p->get_mmu())
110 #define RS1 p->get_state()->XPR[insn.rs1()]
111 #define RS2 p->get_state()->XPR[insn.rs2()]
112 #define RD p->get_state()->XPR.write_port(insn.rd())
113 #define FRS1 p->get_state()->FPR[insn.rs1()]
114 #define FRS2 p->get_state()->FPR[insn.rs2()]
115 #define FRS3 p->get_state()->FPR[insn.rs3()]
116 #define FRD p->get_state()->FPR.write_port(insn.rd())
117 #define SHAMT (insn.i_imm() & 0x3F)
118 #define BRANCH_TARGET (pc + insn.sb_imm())
119 #define JUMP_TARGET (pc + insn.uj_imm())
120 #define RM ({ int rm = insn.rm(); \
121 if(rm == 7) rm = (p->get_state()->fsr & FSR_RD) >> FSR_RD_SHIFT; \
122 if(rm > 4) throw trap_illegal_instruction(); \
125 #define xpr64 (xprlen == 64)
127 #define require_supervisor if(unlikely(!(p->get_state()->sr & SR_S))) throw trap_privileged_instruction()
128 #define require_xpr64 if(unlikely(!xpr64)) throw trap_illegal_instruction()
129 #define require_xpr32 if(unlikely(xpr64)) throw trap_illegal_instruction()
130 #ifndef RISCV_ENABLE_FPU
131 # define require_fp throw trap_illegal_instruction()
133 # define require_fp if(unlikely(!(p->get_state()->sr & SR_EF))) throw trap_fp_disabled()
136 #define cmp_trunc(reg) (reg_t(reg) << (64-xprlen))
137 #define set_fp_exceptions ({ p->set_fsr(p->get_state()->fsr | \
138 (softfloat_exceptionFlags << FSR_AEXC_SHIFT)); \
139 softfloat_exceptionFlags = 0; })
141 #define sext32(x) ((sreg_t)(int32_t)(x))
142 #define zext32(x) ((reg_t)(uint32_t)(x))
143 #define sext_xprlen(x) (((sreg_t)(x) << (64-xprlen)) >> (64-xprlen))
144 #define zext_xprlen(x) (((reg_t)(x) << (64-xprlen)) >> (64-xprlen))
146 #define insn_length(x) \
147 (((x) & 0x03) < 0x03 ? 2 : \
148 ((x) & 0x1f) < 0x1f ? 4 : \
149 ((x) & 0x3f) < 0x3f ? 6 : \
153 do { if ((x) & 3 /* For now... */) \
154 throw trap_instruction_address_misaligned(); \