riscv/disasm.cc

   1 // See LICENSE for license details.
   2
   3 #include "disasm.h"
   4 #include <string>
   5 #include <vector>
   6 #include <cstdarg>
   7 #include <sstream>
   8 #include <stdlib.h>
   9
  10 static const char* xpr[] = {
  11   "zero", "ra", "s0", "s1",  "s2",  "s3",  "s4",  "s5",
  12   "s6",   "s7", "s8", "s9", "s10", "s11",  "sp",  "tp",
  13   "v0",   "v1", "a0", "a1",  "a2",  "a3",  "a4",  "a5",
  14   "a6",   "a7", "t0", "t1",  "t2",  "t3",  "t4",  "gp"
  15 };
  16
  17 static const char* fpr[] = {
  18   "fs0", "fs1",  "fs2",  "fs3",  "fs4",  "fs5",  "fs6",  "fs7",
  19   "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15",
  20   "fv0", "fv1", "fa0",   "fa1",  "fa2",  "fa3",  "fa4",  "fa5",
  21   "fa6", "fa7", "ft0",   "ft1",  "ft2",  "ft3",  "ft4",  "ft5"
  22 };
  23
  24 struct : public arg_t {
  25   std::string to_string(insn_t insn) const {
  26     return std::to_string((int)insn.i_imm()) + '(' + xpr[insn.rs1()] + ')';
  27   }
  28 } load_address;
  29
  30 struct : public arg_t {
  31   std::string to_string(insn_t insn) const {
  32     return std::to_string((int)insn.s_imm()) + '(' + xpr[insn.rs1()] + ')';
  33   }
  34 } store_address;
  35
  36 struct : public arg_t {
  37   std::string to_string(insn_t insn) const {
  38     return std::string("0(") + xpr[insn.rs1()] + ')';
  39   }
  40 } amo_address;
  41
  42 struct : public arg_t {
  43   std::string to_string(insn_t insn) const {
  44     return xpr[insn.rd()];
  45   }
  46 } xrd;
  47
  48 struct : public arg_t {
  49   std::string to_string(insn_t insn) const {
  50     return xpr[insn.rs1()];
  51   }
  52 } xrs1;
  53
  54 struct : public arg_t {
  55   std::string to_string(insn_t insn) const {
  56     return xpr[insn.rs2()];
  57   }
  58 } xrs2;
  59
  60 struct : public arg_t {
  61   std::string to_string(insn_t insn) const {
  62     return fpr[insn.rd()];
  63   }
  64 } frd;
  65
  66 struct : public arg_t {
  67   std::string to_string(insn_t insn) const {
  68     return fpr[insn.rs1()];
  69   }
  70 } frs1;
  71
  72 struct : public arg_t {
  73   std::string to_string(insn_t insn) const {
  74     return fpr[insn.rs2()];
  75   }
  76 } frs2;
  77
  78 struct : public arg_t {
  79   std::string to_string(insn_t insn) const {
  80     return fpr[insn.rs3()];
  81   }
  82 } frs3;
  83
  84 struct : public arg_t {
  85   std::string to_string(insn_t insn) const {
  86     return std::string("pcr") + xpr[insn.rs1()];
  87   }
  88 } pcr;
  89
  90 struct : public arg_t {
  91   std::string to_string(insn_t insn) const {
  92     return std::to_string((int)insn.i_imm());
  93   }
  94 } imm;
  95
  96 struct : public arg_t {
  97   std::string to_string(insn_t insn) const {
  98     std::stringstream s;
  99     s << std::hex << "0x" << ((uint32_t)insn.u_imm() >> 12);
 100     return s.str();
 101   }
 102 } bigimm;
 103
 104 struct : public arg_t {
 105   std::string to_string(insn_t insn) const {
 106     std::stringstream s;
 107     int32_t target = insn.sb_imm();
 108     char sign = target >= 0 ? '+' : '-';
 109     s << "pc " << sign << ' ' << abs(target);
 110     return s.str();
 111   }
 112 } branch_target;
 113
 114 struct : public arg_t {
 115   std::string to_string(insn_t insn) const {
 116     std::stringstream s;
 117     int32_t target = insn.sb_imm();
 118     char sign = target >= 0 ? '+' : '-';
 119     s << "pc " << sign << std::hex << " 0x" << abs(target);
 120     return s.str();
 121   }
 122 } jump_target;
 123
 124 std::string disassembler_t::disassemble(insn_t insn)
 125 {
 126   const disasm_insn_t* disasm_insn = lookup(insn);
 127   return disasm_insn ? disasm_insn->to_string(insn) : "unknown";
 128 }
 129
 130 disassembler_t::disassembler_t()
 131 {
 132   const uint32_t mask_rd = 0x1fUL << 7;
 133   const uint32_t match_rd_ra = 1UL << 7;
 134   const uint32_t mask_rs1 = 0x1fUL << 15;
 135   const uint32_t match_rs1_ra = 1UL << 15;
 136   const uint32_t mask_rs2 = 0x1fUL << 15;
 137   const uint32_t mask_imm = 0xfffUL << 20;
 138
 139   #define DECLARE_INSN(code, match, mask) \
 140    const uint32_t match_##code = match; \
 141    const uint32_t mask_##code = mask;
 142   #include "opcodes.h"
 143   #undef DECLARE_INSN
 144
 145   // explicit per-instruction disassembly
 146   #define DISASM_INSN(name, code, extra, ...) \
 147     add_insn(new disasm_insn_t(name, match_##code, mask_##code | (extra), __VA_ARGS__));
 148   #define DEFINE_NOARG(code) \
 149     add_insn(new disasm_insn_t(#code, match_##code, mask_##code, {}));
 150   #define DEFINE_DTYPE(code) DISASM_INSN(#code, code, 0, {&xrd})
 151   #define DEFINE_RTYPE(code) DISASM_INSN(#code, code, 0, {&xrd, &xrs1, &xrs2})
 152   #define DEFINE_ITYPE(code) DISASM_INSN(#code, code, 0, {&xrd, &xrs1, &imm})
 153   #define DEFINE_I0TYPE(name, code) DISASM_INSN(name, code, mask_rs1, {&xrd, &imm})
 154   #define DEFINE_I1TYPE(name, code) DISASM_INSN(name, code, mask_imm, {&xrd, &xrs1})
 155   #define DEFINE_I2TYPE(name, code) DISASM_INSN(name, code, mask_rd | mask_imm, {&xrs1})
 156   #define DEFINE_LTYPE(code) DISASM_INSN(#code, code, 0, {&xrd, &bigimm})
 157   #define DEFINE_BTYPE(code) DISASM_INSN(#code, code, 0, {&xrs1, &xrs2, &branch_target})
 158   #define DEFINE_B0TYPE(name, code) DISASM_INSN(name, code, mask_rs1 | mask_rs2, {&branch_target})
 159   #define DEFINE_B1TYPE(name, code) DISASM_INSN(name, code, mask_rs2, {&xrs1, &branch_target})
 160   #define DEFINE_XLOAD(code) DISASM_INSN(#code, code, 0, {&xrd, &load_address})
 161   #define DEFINE_XSTORE(code) DISASM_INSN(#code, code, 0, {&xrs2, &store_address})
 162   #define DEFINE_XAMO(code) DISASM_INSN(#code, code, 0, {&xrd, &xrs2, &amo_address})
 163   #define DEFINE_FLOAD(code) DISASM_INSN(#code, code, 0, {&frd, &load_address})
 164   #define DEFINE_FSTORE(code) DISASM_INSN(#code, code, 0, {&frs2, &store_address})
 165   #define DEFINE_FRTYPE(code) DISASM_INSN(#code, code, 0, {&frd, &frs1, &frs2})
 166   #define DEFINE_FR1TYPE(code) DISASM_INSN(#code, code, 0, {&frd, &frs1})
 167   #define DEFINE_FR3TYPE(code) DISASM_INSN(#code, code, 0, {&frd, &frs1, &frs2, &frs3})
 168   #define DEFINE_FXTYPE(code) DISASM_INSN(#code, code, 0, {&xrd, &frs1})
 169   #define DEFINE_XFTYPE(code) DISASM_INSN(#code, code, 0, {&frd, &xrs1})
 170
 171   DEFINE_XLOAD(lb)
 172   DEFINE_XLOAD(lbu)
 173   DEFINE_XLOAD(lh)
 174   DEFINE_XLOAD(lhu)
 175   DEFINE_XLOAD(lw)
 176   DEFINE_XLOAD(lwu)
 177   DEFINE_XLOAD(ld)
 178
 179   DEFINE_XSTORE(sb)
 180   DEFINE_XSTORE(sh)
 181   DEFINE_XSTORE(sw)
 182   DEFINE_XSTORE(sd)
 183
 184   DEFINE_XAMO(amoadd_w)
 185   DEFINE_XAMO(amoswap_w)
 186   DEFINE_XAMO(amoand_w)
 187   DEFINE_XAMO(amoor_w)
 188   DEFINE_XAMO(amomin_w)
 189   DEFINE_XAMO(amomax_w)
 190   DEFINE_XAMO(amominu_w)
 191   DEFINE_XAMO(amomaxu_w)
 192   DEFINE_XAMO(amoadd_d)
 193   DEFINE_XAMO(amoswap_d)
 194   DEFINE_XAMO(amoand_d)
 195   DEFINE_XAMO(amoor_d)
 196   DEFINE_XAMO(amomin_d)
 197   DEFINE_XAMO(amomax_d)
 198   DEFINE_XAMO(amominu_d)
 199   DEFINE_XAMO(amomaxu_d)
 200
 201   DEFINE_XAMO(lr_w)
 202   DEFINE_XAMO(sc_w)
 203   DEFINE_XAMO(lr_d)
 204   DEFINE_XAMO(sc_d)
 205
 206   DEFINE_FLOAD(flw)
 207   DEFINE_FLOAD(fld)
 208
 209   DEFINE_FSTORE(fsw)
 210   DEFINE_FSTORE(fsd)
 211
 212   add_insn(new disasm_insn_t("j", match_jal, mask_jal | mask_rd, {&jump_target}));
 213   add_insn(new disasm_insn_t("jal", match_jal | match_rd_ra, mask_jal | mask_rd, {&jump_target}));
 214   add_insn(new disasm_insn_t("jal", match_jal, mask_jal, {&xrd, &jump_target}));
 215
 216   DEFINE_B0TYPE("b",    beq);
 217   DEFINE_B1TYPE("beqz", beq);
 218   DEFINE_B1TYPE("bnez", bne);
 219   DEFINE_B1TYPE("bltz", blt);
 220   DEFINE_B1TYPE("bgez", bge);
 221   DEFINE_BTYPE(beq)
 222   DEFINE_BTYPE(bne)
 223   DEFINE_BTYPE(blt)
 224   DEFINE_BTYPE(bge)
 225   DEFINE_BTYPE(bltu)
 226   DEFINE_BTYPE(bgeu)
 227
 228   DEFINE_LTYPE(lui);
 229   DEFINE_LTYPE(auipc);
 230
 231   DEFINE_I2TYPE("jr", jalr);
 232   add_insn(new disasm_insn_t("jalr", match_jalr | match_rd_ra, mask_jalr | mask_rd | mask_imm, {&xrs1}));
 233   add_insn(new disasm_insn_t("ret", match_jalr | match_rs1_ra, mask_jalr | mask_rd | mask_rs1 | mask_imm, {}));
 234   DEFINE_ITYPE(jalr);
 235
 236   add_insn(new disasm_insn_t("nop", match_addi, mask_addi | mask_rd | mask_rs1 | mask_imm, {}));
 237   DEFINE_I0TYPE("li", addi);
 238   DEFINE_I1TYPE("move", addi);
 239   DEFINE_ITYPE(addi);
 240   DEFINE_ITYPE(slli);
 241   DEFINE_ITYPE(slti);
 242   DEFINE_ITYPE(sltiu);
 243   DEFINE_ITYPE(xori);
 244   DEFINE_ITYPE(srli);
 245   DEFINE_ITYPE(srai);
 246   DEFINE_ITYPE(ori);
 247   DEFINE_ITYPE(andi);
 248   DEFINE_ITYPE(addiw);
 249   DEFINE_ITYPE(slliw);
 250   DEFINE_ITYPE(srliw);
 251   DEFINE_ITYPE(sraiw);
 252
 253   DEFINE_RTYPE(add);
 254   DEFINE_RTYPE(sub);
 255   DEFINE_RTYPE(sll);
 256   DEFINE_RTYPE(slt);
 257   DEFINE_RTYPE(sltu);
 258   DEFINE_RTYPE(xor);
 259   DEFINE_RTYPE(srl);
 260   DEFINE_RTYPE(sra);
 261   DEFINE_RTYPE(or);
 262   DEFINE_RTYPE(and);
 263   DEFINE_RTYPE(mul);
 264   DEFINE_RTYPE(mulh);
 265   DEFINE_RTYPE(mulhu);
 266   DEFINE_RTYPE(mulhsu);
 267   DEFINE_RTYPE(div);
 268   DEFINE_RTYPE(divu);
 269   DEFINE_RTYPE(rem);
 270   DEFINE_RTYPE(remu);
 271   DEFINE_RTYPE(addw);
 272   DEFINE_RTYPE(subw);
 273   DEFINE_RTYPE(sllw);
 274   DEFINE_RTYPE(srlw);
 275   DEFINE_RTYPE(sraw);
 276   DEFINE_RTYPE(mulw);
 277   DEFINE_RTYPE(divw);
 278   DEFINE_RTYPE(divuw);
 279   DEFINE_RTYPE(remw);
 280   DEFINE_RTYPE(remuw);
 281
 282   DEFINE_NOARG(syscall);
 283   DEFINE_NOARG(break);
 284   DEFINE_NOARG(fence);
 285   DEFINE_NOARG(fence_i);
 286
 287   DEFINE_DTYPE(rdcycle);
 288   DEFINE_DTYPE(rdtime);
 289   DEFINE_DTYPE(rdinstret);
 290
 291   add_insn(new disasm_insn_t("mtpcr", match_mtpcr, mask_mtpcr | mask_rd, {&xrs2, &pcr}));
 292   add_insn(new disasm_insn_t("mtpcr", match_mtpcr, mask_mtpcr, {&xrd, &xrs2, &pcr}));
 293   add_insn(new disasm_insn_t("mfpcr", match_mfpcr, mask_mfpcr, {&xrd, &pcr}));
 294   add_insn(new disasm_insn_t("setpcr", match_setpcr, mask_setpcr, {&xrd, &pcr, &imm}));
 295   add_insn(new disasm_insn_t("clearpcr", match_clearpcr, mask_clearpcr, {&xrd, &pcr, &imm}));
 296   DEFINE_NOARG(eret)
 297
 298   DEFINE_FRTYPE(fadd_s);
 299   DEFINE_FRTYPE(fsub_s);
 300   DEFINE_FRTYPE(fmul_s);
 301   DEFINE_FRTYPE(fdiv_s);
 302   DEFINE_FR1TYPE(fsqrt_s);
 303   DEFINE_FRTYPE(fmin_s);
 304   DEFINE_FRTYPE(fmax_s);
 305   DEFINE_FR3TYPE(fmadd_s);
 306   DEFINE_FR3TYPE(fmsub_s);
 307   DEFINE_FR3TYPE(fnmadd_s);
 308   DEFINE_FR3TYPE(fnmsub_s);
 309   DEFINE_FRTYPE(fsgnj_s);
 310   DEFINE_FRTYPE(fsgnjn_s);
 311   DEFINE_FRTYPE(fsgnjx_s);
 312   DEFINE_FR1TYPE(fcvt_s_d);
 313   DEFINE_XFTYPE(fcvt_s_l);
 314   DEFINE_XFTYPE(fcvt_s_lu);
 315   DEFINE_XFTYPE(fcvt_s_w);
 316   DEFINE_XFTYPE(fcvt_s_wu);
 317   DEFINE_XFTYPE(fcvt_s_wu);
 318   DEFINE_XFTYPE(fmv_s_x);
 319   DEFINE_FXTYPE(fcvt_l_s);
 320   DEFINE_FXTYPE(fcvt_lu_s);
 321   DEFINE_FXTYPE(fcvt_w_s);
 322   DEFINE_FXTYPE(fcvt_wu_s);
 323   DEFINE_FXTYPE(fmv_x_s);
 324   DEFINE_FXTYPE(feq_s);
 325   DEFINE_FXTYPE(flt_s);
 326   DEFINE_FXTYPE(fle_s);
 327
 328   DEFINE_FRTYPE(fadd_d);
 329   DEFINE_FRTYPE(fsub_d);
 330   DEFINE_FRTYPE(fmul_d);
 331   DEFINE_FRTYPE(fdiv_d);
 332   DEFINE_FR1TYPE(fsqrt_d);
 333   DEFINE_FRTYPE(fmin_d);
 334   DEFINE_FRTYPE(fmax_d);
 335   DEFINE_FR3TYPE(fmadd_d);
 336   DEFINE_FR3TYPE(fmsub_d);
 337   DEFINE_FR3TYPE(fnmadd_d);
 338   DEFINE_FR3TYPE(fnmsub_d);
 339   DEFINE_FRTYPE(fsgnj_d);
 340   DEFINE_FRTYPE(fsgnjn_d);
 341   DEFINE_FRTYPE(fsgnjx_d);
 342   DEFINE_FR1TYPE(fcvt_d_s);
 343   DEFINE_XFTYPE(fcvt_d_l);
 344   DEFINE_XFTYPE(fcvt_d_lu);
 345   DEFINE_XFTYPE(fcvt_d_w);
 346   DEFINE_XFTYPE(fcvt_d_wu);
 347   DEFINE_XFTYPE(fcvt_d_wu);
 348   DEFINE_XFTYPE(fmv_d_x);
 349   DEFINE_FXTYPE(fcvt_l_d);
 350   DEFINE_FXTYPE(fcvt_lu_d);
 351   DEFINE_FXTYPE(fcvt_w_d);
 352   DEFINE_FXTYPE(fcvt_wu_d);
 353   DEFINE_FXTYPE(fmv_x_d);
 354   DEFINE_FXTYPE(feq_d);
 355   DEFINE_FXTYPE(flt_d);
 356   DEFINE_FXTYPE(fle_d);
 357
 358   add_insn(new disasm_insn_t("fssr", match_fssr, mask_fssr | mask_rd, {&xrs1}));
 359   add_insn(new disasm_insn_t("fssr", match_fssr, mask_fssr, {&xrd, &xrs1}));
 360   DEFINE_DTYPE(frsr);
 361
 362   // provide a default disassembly for all instructions as a fallback
 363   #define DECLARE_INSN(code, match, mask) \
 364    add_insn(new disasm_insn_t(#code " (args unknown)", match, mask, {}));
 365   #include "opcodes.h"
 366   #undef DECLARE_INSN
 367 }
 368
 369 const disasm_insn_t* disassembler_t::lookup(insn_t insn)
 370 {
 371   size_t idx = insn.bits() % HASH_SIZE;
 372   for (size_t j = 0; j < chain[idx].size(); j++)
 373     if(*chain[idx][j] == insn)
 374       return chain[idx][j];
 375
 376   idx = HASH_SIZE;
 377   for (size_t j = 0; j < chain[idx].size(); j++)
 378     if(*chain[idx][j] == insn)
 379       return chain[idx][j];
 380
 381   return NULL;
 382 }
 383
 384 void disassembler_t::add_insn(disasm_insn_t* insn)
 385 {
 386   size_t idx = HASH_SIZE;
 387   if (insn->get_mask() % HASH_SIZE == HASH_SIZE - 1)
 388     idx = insn->get_match() % HASH_SIZE;
 389   chain[idx].push_back(insn);
 390 }
 391
 392 disassembler_t::~disassembler_t()
 393 {
 394   for (size_t i = 0; i < HASH_SIZE+1; i++)
 395     for (size_t j = 0; j < chain[i].size(); j++)
 396       delete chain[i][j];
 397 }