1 // See LICENSE for license details.
3 #ifndef RISCV_CSR_ENCODING_H
4 #define RISCV_CSR_ENCODING_H
6 #define SR_S 0x00000001
7 #define SR_PS 0x00000002
8 #define SR_EI 0x00000004
9 #define SR_PEI 0x00000008
10 #define SR_EF 0x00000010
11 #define SR_U64 0x00000020
12 #define SR_S64 0x00000040
13 #define SR_VM 0x00000080
14 #define SR_EA 0x00000100
15 #define SR_IM 0x00FF0000
16 #define SR_IP 0xFF000000
17 #define SR_ZERO ~(SR_S|SR_PS|SR_EI|SR_PEI|SR_EF|SR_U64|SR_S64|SR_VM|SR_EA|SR_IM|SR_IP)
18 #define SR_IM_SHIFT 16
19 #define SR_IP_SHIFT 24
29 #define CAUSE_MISALIGNED_FETCH 0
30 #define CAUSE_FAULT_FETCH 1
31 #define CAUSE_ILLEGAL_INSTRUCTION 2
32 #define CAUSE_PRIVILEGED_INSTRUCTION 3
33 #define CAUSE_FP_DISABLED 4
34 #define CAUSE_SYSCALL 6
35 #define CAUSE_BREAKPOINT 7
36 #define CAUSE_MISALIGNED_LOAD 8
37 #define CAUSE_MISALIGNED_STORE 9
38 #define CAUSE_FAULT_LOAD 10
39 #define CAUSE_FAULT_STORE 11
40 #define CAUSE_ACCELERATOR_DISABLED 12
42 // page table entry (PTE) fields
43 #define PTE_V 0x001 // Entry is a page Table descriptor
44 #define PTE_T 0x002 // Entry is a page Table, not a terminal node
45 #define PTE_G 0x004 // Global
46 #define PTE_UR 0x008 // User Write permission
47 #define PTE_UW 0x010 // User Read permission
48 #define PTE_UX 0x020 // User eXecute permission
49 #define PTE_SR 0x040 // Supervisor Read permission
50 #define PTE_SW 0x080 // Supervisor Write permission
51 #define PTE_SX 0x100 // Supervisor eXecute permission
52 #define PTE_PERM (PTE_SR | PTE_SW | PTE_SX | PTE_UR | PTE_UW | PTE_UX)
57 # define RISCV_PGLEVELS 3
58 # define RISCV_PGSHIFT 13
60 # define RISCV_PGLEVELS 2
61 # define RISCV_PGSHIFT 12
63 #define RISCV_PGLEVEL_BITS 10
64 #define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
68 #define read_csr(reg) ({ long __tmp; \
69 asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
72 #define write_csr(reg, val) \
73 asm volatile ("csrw " #reg ", %0" :: "r"(val))
75 #define swap_csr(reg, val) ({ long __tmp; \
76 asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
79 #define set_csr(reg, bit) ({ long __tmp; \
80 if (__builtin_constant_p(bit) && (bit) < 32) \
81 asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
83 asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
86 #define clear_csr(reg, bit) ({ long __tmp; \
87 if (__builtin_constant_p(bit) && (bit) < 32) \
88 asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
90 asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
93 #define rdcycle() ({ unsigned long __tmp; \
94 asm volatile ("rdcycle %0" : "=r"(__tmp)); \
102 /* Automatically generated by parse-opcodes */
103 #ifndef RISCV_ENCODING_H
104 #define RISCV_ENCODING_H
105 #define MATCH_FMV_S_X 0xf0000053
106 #define MASK_FMV_S_X 0xfff0707f
107 #define MATCH_AMOXOR_W 0x2000202f
108 #define MASK_AMOXOR_W 0xf800707f
109 #define MATCH_REMUW 0x200703b
110 #define MASK_REMUW 0xfe00707f
111 #define MATCH_FMIN_D 0xc2000053
112 #define MASK_FMIN_D 0xfe00707f
113 #define MATCH_AMOMAX_D 0xa000302f
114 #define MASK_AMOMAX_D 0xf800707f
115 #define MATCH_BLTU 0x6063
116 #define MASK_BLTU 0x707f
117 #define MATCH_FSGNJN_D 0x32000053
118 #define MASK_FSGNJN_D 0xfe00707f
119 #define MATCH_FMIN_S 0xc0000053
120 #define MASK_FMIN_S 0xfe00707f
121 #define MATCH_CSRRW 0x1073
122 #define MASK_CSRRW 0x707f
123 #define MATCH_SLLIW 0x101b
124 #define MASK_SLLIW 0xfe00707f
126 #define MASK_LB 0x707f
127 #define MATCH_FCVT_D_L 0x62000053
128 #define MASK_FCVT_D_L 0xfff0007f
129 #define MATCH_LH 0x1003
130 #define MASK_LH 0x707f
131 #define MATCH_FCVT_D_W 0x72000053
132 #define MASK_FCVT_D_W 0xfff0007f
133 #define MATCH_LW 0x2003
134 #define MASK_LW 0x707f
135 #define MATCH_ADD 0x33
136 #define MASK_ADD 0xfe00707f
137 #define MATCH_CSRRC 0x3073
138 #define MASK_CSRRC 0x707f
139 #define MATCH_FMAX_D 0xca000053
140 #define MASK_FMAX_D 0xfe00707f
141 #define MATCH_BNE 0x1063
142 #define MASK_BNE 0x707f
143 #define MATCH_FCVT_S_D 0x88000053
144 #define MASK_FCVT_S_D 0xfff0007f
145 #define MATCH_BGEU 0x7063
146 #define MASK_BGEU 0x707f
147 #define MATCH_FADD_D 0x2000053
148 #define MASK_FADD_D 0xfe00007f
149 #define MATCH_SLTIU 0x3013
150 #define MASK_SLTIU 0x707f
151 #define MATCH_FADD_S 0x53
152 #define MASK_FADD_S 0xfe00007f
153 #define MATCH_FCVT_S_W 0x70000053
154 #define MASK_FCVT_S_W 0xfff0007f
155 #define MATCH_MUL 0x2000033
156 #define MASK_MUL 0xfe00707f
157 #define MATCH_AMOMINU_D 0xc000302f
158 #define MASK_AMOMINU_D 0xf800707f
159 #define MATCH_FCVT_S_LU 0x68000053
160 #define MASK_FCVT_S_LU 0xfff0007f
161 #define MATCH_SRLI 0x5013
162 #define MASK_SRLI 0xfc00707f
163 #define MATCH_AMOMINU_W 0xc000202f
164 #define MASK_AMOMINU_W 0xf800707f
165 #define MATCH_DIVUW 0x200503b
166 #define MASK_DIVUW 0xfe00707f
167 #define MATCH_MULW 0x200003b
168 #define MASK_MULW 0xfe00707f
169 #define MATCH_SRLW 0x503b
170 #define MASK_SRLW 0xfe00707f
171 #define MATCH_DIV 0x2004033
172 #define MASK_DIV 0xfe00707f
173 #define MATCH_FDIV_D 0x1a000053
174 #define MASK_FDIV_D 0xfe00007f
175 #define MATCH_FENCE 0xf
176 #define MASK_FENCE 0x707f
177 #define MATCH_FNMSUB_S 0x4b
178 #define MASK_FNMSUB_S 0x600007f
179 #define MATCH_FCVT_L_S 0x40000053
180 #define MASK_FCVT_L_S 0xfff0007f
181 #define MATCH_SBREAK 0x100073
182 #define MASK_SBREAK 0xffffffff
183 #define MATCH_FLE_S 0xb8000053
184 #define MASK_FLE_S 0xfe00707f
185 #define MATCH_FDIV_S 0x18000053
186 #define MASK_FDIV_S 0xfe00007f
187 #define MATCH_FLE_D 0xba000053
188 #define MASK_FLE_D 0xfe00707f
189 #define MATCH_FENCE_I 0x100f
190 #define MASK_FENCE_I 0x707f
191 #define MATCH_FNMSUB_D 0x200004b
192 #define MASK_FNMSUB_D 0x600007f
193 #define MATCH_ADDW 0x3b
194 #define MASK_ADDW 0xfe00707f
195 #define MATCH_SLL 0x1033
196 #define MASK_SLL 0xfe00707f
197 #define MATCH_XOR 0x4033
198 #define MASK_XOR 0xfe00707f
199 #define MATCH_SUB 0x40000033
200 #define MASK_SUB 0xfe00707f
201 #define MATCH_BLT 0x4063
202 #define MASK_BLT 0x707f
203 #define MATCH_SCALL 0x73
204 #define MASK_SCALL 0xffffffff
205 #define MATCH_SC_W 0x1800202f
206 #define MASK_SC_W 0xf800707f
207 #define MATCH_REM 0x2006033
208 #define MASK_REM 0xfe00707f
209 #define MATCH_SRLIW 0x501b
210 #define MASK_SRLIW 0xfe00707f
211 #define MATCH_LUI 0x37
212 #define MASK_LUI 0x7f
213 #define MATCH_CSRRCI 0x7073
214 #define MASK_CSRRCI 0x707f
215 #define MATCH_ADDI 0x13
216 #define MASK_ADDI 0x707f
217 #define MATCH_MULH 0x2001033
218 #define MASK_MULH 0xfe00707f
219 #define MATCH_FMUL_S 0x10000053
220 #define MASK_FMUL_S 0xfe00007f
221 #define MATCH_CSRRSI 0x6073
222 #define MASK_CSRRSI 0x707f
223 #define MATCH_SRAI 0x40005013
224 #define MASK_SRAI 0xfc00707f
225 #define MATCH_AMOAND_D 0x6000302f
226 #define MASK_AMOAND_D 0xf800707f
227 #define MATCH_FLT_D 0xb2000053
228 #define MASK_FLT_D 0xfe00707f
229 #define MATCH_SRAW 0x4000503b
230 #define MASK_SRAW 0xfe00707f
231 #define MATCH_FMUL_D 0x12000053
232 #define MASK_FMUL_D 0xfe00007f
233 #define MATCH_LD 0x3003
234 #define MASK_LD 0x707f
235 #define MATCH_ORI 0x6013
236 #define MASK_ORI 0x707f
237 #define MATCH_CSRRS 0x2073
238 #define MASK_CSRRS 0x707f
239 #define MATCH_FLT_S 0xb0000053
240 #define MASK_FLT_S 0xfe00707f
241 #define MATCH_ADDIW 0x1b
242 #define MASK_ADDIW 0x707f
243 #define MATCH_AMOAND_W 0x6000202f
244 #define MASK_AMOAND_W 0xf800707f
245 #define MATCH_FEQ_S 0xa8000053
246 #define MASK_FEQ_S 0xfe00707f
247 #define MATCH_FSGNJX_D 0x3a000053
248 #define MASK_FSGNJX_D 0xfe00707f
249 #define MATCH_SRA 0x40005033
250 #define MASK_SRA 0xfe00707f
251 #define MATCH_BGE 0x5063
252 #define MASK_BGE 0x707f
253 #define MATCH_SRAIW 0x4000501b
254 #define MASK_SRAIW 0xfe00707f
255 #define MATCH_SRL 0x5033
256 #define MASK_SRL 0xfe00707f
257 #define MATCH_FSUB_D 0xa000053
258 #define MASK_FSUB_D 0xfe00007f
259 #define MATCH_FSGNJX_S 0x38000053
260 #define MASK_FSGNJX_S 0xfe00707f
261 #define MATCH_FEQ_D 0xaa000053
262 #define MASK_FEQ_D 0xfe00707f
263 #define MATCH_FCVT_D_WU 0x7a000053
264 #define MASK_FCVT_D_WU 0xfff0007f
265 #define MATCH_OR 0x6033
266 #define MASK_OR 0xfe00707f
267 #define MATCH_FCVT_WU_D 0x5a000053
268 #define MASK_FCVT_WU_D 0xfff0007f
269 #define MATCH_SUBW 0x4000003b
270 #define MASK_SUBW 0xfe00707f
271 #define MATCH_FMAX_S 0xc8000053
272 #define MASK_FMAX_S 0xfe00707f
273 #define MATCH_AMOMAXU_D 0xe000302f
274 #define MASK_AMOMAXU_D 0xf800707f
275 #define MATCH_XORI 0x4013
276 #define MASK_XORI 0x707f
277 #define MATCH_AMOXOR_D 0x2000302f
278 #define MASK_AMOXOR_D 0xf800707f
279 #define MATCH_AMOMAXU_W 0xe000202f
280 #define MASK_AMOMAXU_W 0xf800707f
281 #define MATCH_FCVT_WU_S 0x58000053
282 #define MASK_FCVT_WU_S 0xfff0007f
283 #define MATCH_ANDI 0x7013
284 #define MASK_ANDI 0x707f
285 #define MATCH_FMV_X_S 0xe0000053
286 #define MASK_FMV_X_S 0xfff0707f
287 #define MATCH_SRET 0x80000073
288 #define MASK_SRET 0xffffffff
289 #define MATCH_FNMADD_S 0x4f
290 #define MASK_FNMADD_S 0x600007f
291 #define MATCH_JAL 0x6f
292 #define MASK_JAL 0x7f
293 #define MATCH_LWU 0x6003
294 #define MASK_LWU 0x707f
295 #define MATCH_FMV_X_D 0xe2000053
296 #define MASK_FMV_X_D 0xfff0707f
297 #define MATCH_FCVT_D_S 0x82000053
298 #define MASK_FCVT_D_S 0xfff0007f
299 #define MATCH_FNMADD_D 0x200004f
300 #define MASK_FNMADD_D 0x600007f
301 #define MATCH_AMOADD_D 0x302f
302 #define MASK_AMOADD_D 0xf800707f
303 #define MATCH_LR_D 0x1000302f
304 #define MASK_LR_D 0xf9f0707f
305 #define MATCH_FCVT_W_S 0x50000053
306 #define MASK_FCVT_W_S 0xfff0007f
307 #define MATCH_MULHSU 0x2002033
308 #define MASK_MULHSU 0xfe00707f
309 #define MATCH_AMOADD_W 0x202f
310 #define MASK_AMOADD_W 0xf800707f
311 #define MATCH_FCVT_D_LU 0x6a000053
312 #define MASK_FCVT_D_LU 0xfff0007f
313 #define MATCH_LR_W 0x1000202f
314 #define MASK_LR_W 0xf9f0707f
315 #define MATCH_FCVT_W_D 0x52000053
316 #define MASK_FCVT_W_D 0xfff0007f
317 #define MATCH_SLT 0x2033
318 #define MASK_SLT 0xfe00707f
319 #define MATCH_SLLW 0x103b
320 #define MASK_SLLW 0xfe00707f
321 #define MATCH_AMOOR_D 0x4000302f
322 #define MASK_AMOOR_D 0xf800707f
323 #define MATCH_SLTI 0x2013
324 #define MASK_SLTI 0x707f
325 #define MATCH_REMU 0x2007033
326 #define MASK_REMU 0xfe00707f
327 #define MATCH_FLW 0x2007
328 #define MASK_FLW 0x707f
329 #define MATCH_REMW 0x200603b
330 #define MASK_REMW 0xfe00707f
331 #define MATCH_SLTU 0x3033
332 #define MASK_SLTU 0xfe00707f
333 #define MATCH_SLLI 0x1013
334 #define MASK_SLLI 0xfc00707f
335 #define MATCH_AMOOR_W 0x4000202f
336 #define MASK_AMOOR_W 0xf800707f
337 #define MATCH_BEQ 0x63
338 #define MASK_BEQ 0x707f
339 #define MATCH_FLD 0x3007
340 #define MASK_FLD 0x707f
341 #define MATCH_FSUB_S 0x8000053
342 #define MASK_FSUB_S 0xfe00007f
343 #define MATCH_AND 0x7033
344 #define MASK_AND 0xfe00707f
345 #define MATCH_FMV_D_X 0xf2000053
346 #define MASK_FMV_D_X 0xfff0707f
347 #define MATCH_LBU 0x4003
348 #define MASK_LBU 0x707f
349 #define MATCH_FSGNJ_S 0x28000053
350 #define MASK_FSGNJ_S 0xfe00707f
351 #define MATCH_AMOMAX_W 0xa000202f
352 #define MASK_AMOMAX_W 0xf800707f
353 #define MATCH_FSGNJ_D 0x2a000053
354 #define MASK_FSGNJ_D 0xfe00707f
355 #define MATCH_MULHU 0x2003033
356 #define MASK_MULHU 0xfe00707f
357 #define MATCH_FCVT_L_D 0x42000053
358 #define MASK_FCVT_L_D 0xfff0007f
359 #define MATCH_FCVT_S_WU 0x78000053
360 #define MASK_FCVT_S_WU 0xfff0007f
361 #define MATCH_FCVT_LU_S 0x48000053
362 #define MASK_FCVT_LU_S 0xfff0007f
363 #define MATCH_FCVT_S_L 0x60000053
364 #define MASK_FCVT_S_L 0xfff0007f
365 #define MATCH_AUIPC 0x17
366 #define MASK_AUIPC 0x7f
367 #define MATCH_FCVT_LU_D 0x4a000053
368 #define MASK_FCVT_LU_D 0xfff0007f
369 #define MATCH_CSRRWI 0x5073
370 #define MASK_CSRRWI 0x707f
371 #define MATCH_SC_D 0x1800302f
372 #define MASK_SC_D 0xf800707f
373 #define MATCH_FMADD_S 0x43
374 #define MASK_FMADD_S 0x600007f
375 #define MATCH_FSQRT_S 0x20000053
376 #define MASK_FSQRT_S 0xfff0007f
377 #define MATCH_AMOMIN_W 0x8000202f
378 #define MASK_AMOMIN_W 0xf800707f
379 #define MATCH_FSGNJN_S 0x30000053
380 #define MASK_FSGNJN_S 0xfe00707f
381 #define MATCH_AMOSWAP_D 0x800302f
382 #define MASK_AMOSWAP_D 0xf800707f
383 #define MATCH_FSQRT_D 0x22000053
384 #define MASK_FSQRT_D 0xfff0007f
385 #define MATCH_FMADD_D 0x2000043
386 #define MASK_FMADD_D 0x600007f
387 #define MATCH_DIVW 0x200403b
388 #define MASK_DIVW 0xfe00707f
389 #define MATCH_AMOMIN_D 0x8000302f
390 #define MASK_AMOMIN_D 0xf800707f
391 #define MATCH_DIVU 0x2005033
392 #define MASK_DIVU 0xfe00707f
393 #define MATCH_AMOSWAP_W 0x800202f
394 #define MASK_AMOSWAP_W 0xf800707f
395 #define MATCH_JALR 0x67
396 #define MASK_JALR 0x707f
397 #define MATCH_FSD 0x3027
398 #define MASK_FSD 0x707f
399 #define MATCH_SW 0x2023
400 #define MASK_SW 0x707f
401 #define MATCH_FMSUB_S 0x47
402 #define MASK_FMSUB_S 0x600007f
403 #define MATCH_LHU 0x5003
404 #define MASK_LHU 0x707f
405 #define MATCH_SH 0x1023
406 #define MASK_SH 0x707f
407 #define MATCH_FSW 0x2027
408 #define MASK_FSW 0x707f
409 #define MATCH_SB 0x23
410 #define MASK_SB 0x707f
411 #define MATCH_FMSUB_D 0x2000047
412 #define MASK_FMSUB_D 0x600007f
413 #define MATCH_SD 0x3023
414 #define MASK_SD 0x707f
415 #define CSR_FFLAGS 0x1
418 #define CSR_SUP0 0x500
419 #define CSR_SUP1 0x501
420 #define CSR_EPC 0x502
421 #define CSR_BADVADDR 0x503
422 #define CSR_PTBR 0x504
423 #define CSR_ASID 0x505
424 #define CSR_COUNT 0x506
425 #define CSR_COMPARE 0x507
426 #define CSR_EVEC 0x508
427 #define CSR_CAUSE 0x509
428 #define CSR_STATUS 0x50a
429 #define CSR_HARTID 0x50b
430 #define CSR_IMPL 0x50c
431 #define CSR_FATC 0x50d
432 #define CSR_SEND_IPI 0x50e
433 #define CSR_CLEAR_IPI 0x50f
434 #define CSR_STATS 0x51c
435 #define CSR_RESET 0x51d
436 #define CSR_TOHOST 0x51e
437 #define CSR_FROMHOST 0x51f
438 #define CSR_CYCLE 0xc00
439 #define CSR_TIME 0xc01
440 #define CSR_INSTRET 0xc02
443 DECLARE_INSN(fmv_s_x
, MATCH_FMV_S_X
, MASK_FMV_S_X
)
444 DECLARE_INSN(amoxor_w
, MATCH_AMOXOR_W
, MASK_AMOXOR_W
)
445 DECLARE_INSN(remuw
, MATCH_REMUW
, MASK_REMUW
)
446 DECLARE_INSN(fmin_d
, MATCH_FMIN_D
, MASK_FMIN_D
)
447 DECLARE_INSN(amomax_d
, MATCH_AMOMAX_D
, MASK_AMOMAX_D
)
448 DECLARE_INSN(bltu
, MATCH_BLTU
, MASK_BLTU
)
449 DECLARE_INSN(fsgnjn_d
, MATCH_FSGNJN_D
, MASK_FSGNJN_D
)
450 DECLARE_INSN(fmin_s
, MATCH_FMIN_S
, MASK_FMIN_S
)
451 DECLARE_INSN(csrrw
, MATCH_CSRRW
, MASK_CSRRW
)
452 DECLARE_INSN(slliw
, MATCH_SLLIW
, MASK_SLLIW
)
453 DECLARE_INSN(lb
, MATCH_LB
, MASK_LB
)
454 DECLARE_INSN(fcvt_d_l
, MATCH_FCVT_D_L
, MASK_FCVT_D_L
)
455 DECLARE_INSN(lh
, MATCH_LH
, MASK_LH
)
456 DECLARE_INSN(fcvt_d_w
, MATCH_FCVT_D_W
, MASK_FCVT_D_W
)
457 DECLARE_INSN(lw
, MATCH_LW
, MASK_LW
)
458 DECLARE_INSN(add
, MATCH_ADD
, MASK_ADD
)
459 DECLARE_INSN(csrrc
, MATCH_CSRRC
, MASK_CSRRC
)
460 DECLARE_INSN(fmax_d
, MATCH_FMAX_D
, MASK_FMAX_D
)
461 DECLARE_INSN(bne
, MATCH_BNE
, MASK_BNE
)
462 DECLARE_INSN(fcvt_s_d
, MATCH_FCVT_S_D
, MASK_FCVT_S_D
)
463 DECLARE_INSN(bgeu
, MATCH_BGEU
, MASK_BGEU
)
464 DECLARE_INSN(fadd_d
, MATCH_FADD_D
, MASK_FADD_D
)
465 DECLARE_INSN(sltiu
, MATCH_SLTIU
, MASK_SLTIU
)
466 DECLARE_INSN(fadd_s
, MATCH_FADD_S
, MASK_FADD_S
)
467 DECLARE_INSN(fcvt_s_w
, MATCH_FCVT_S_W
, MASK_FCVT_S_W
)
468 DECLARE_INSN(mul
, MATCH_MUL
, MASK_MUL
)
469 DECLARE_INSN(amominu_d
, MATCH_AMOMINU_D
, MASK_AMOMINU_D
)
470 DECLARE_INSN(fcvt_s_lu
, MATCH_FCVT_S_LU
, MASK_FCVT_S_LU
)
471 DECLARE_INSN(srli
, MATCH_SRLI
, MASK_SRLI
)
472 DECLARE_INSN(amominu_w
, MATCH_AMOMINU_W
, MASK_AMOMINU_W
)
473 DECLARE_INSN(divuw
, MATCH_DIVUW
, MASK_DIVUW
)
474 DECLARE_INSN(mulw
, MATCH_MULW
, MASK_MULW
)
475 DECLARE_INSN(srlw
, MATCH_SRLW
, MASK_SRLW
)
476 DECLARE_INSN(div
, MATCH_DIV
, MASK_DIV
)
477 DECLARE_INSN(fdiv_d
, MATCH_FDIV_D
, MASK_FDIV_D
)
478 DECLARE_INSN(fence
, MATCH_FENCE
, MASK_FENCE
)
479 DECLARE_INSN(fnmsub_s
, MATCH_FNMSUB_S
, MASK_FNMSUB_S
)
480 DECLARE_INSN(fcvt_l_s
, MATCH_FCVT_L_S
, MASK_FCVT_L_S
)
481 DECLARE_INSN(sbreak
, MATCH_SBREAK
, MASK_SBREAK
)
482 DECLARE_INSN(fle_s
, MATCH_FLE_S
, MASK_FLE_S
)
483 DECLARE_INSN(fdiv_s
, MATCH_FDIV_S
, MASK_FDIV_S
)
484 DECLARE_INSN(fle_d
, MATCH_FLE_D
, MASK_FLE_D
)
485 DECLARE_INSN(fence_i
, MATCH_FENCE_I
, MASK_FENCE_I
)
486 DECLARE_INSN(fnmsub_d
, MATCH_FNMSUB_D
, MASK_FNMSUB_D
)
487 DECLARE_INSN(addw
, MATCH_ADDW
, MASK_ADDW
)
488 DECLARE_INSN(sll
, MATCH_SLL
, MASK_SLL
)
489 DECLARE_INSN(xor, MATCH_XOR
, MASK_XOR
)
490 DECLARE_INSN(sub
, MATCH_SUB
, MASK_SUB
)
491 DECLARE_INSN(blt
, MATCH_BLT
, MASK_BLT
)
492 DECLARE_INSN(scall
, MATCH_SCALL
, MASK_SCALL
)
493 DECLARE_INSN(sc_w
, MATCH_SC_W
, MASK_SC_W
)
494 DECLARE_INSN(rem
, MATCH_REM
, MASK_REM
)
495 DECLARE_INSN(srliw
, MATCH_SRLIW
, MASK_SRLIW
)
496 DECLARE_INSN(lui
, MATCH_LUI
, MASK_LUI
)
497 DECLARE_INSN(csrrci
, MATCH_CSRRCI
, MASK_CSRRCI
)
498 DECLARE_INSN(addi
, MATCH_ADDI
, MASK_ADDI
)
499 DECLARE_INSN(mulh
, MATCH_MULH
, MASK_MULH
)
500 DECLARE_INSN(fmul_s
, MATCH_FMUL_S
, MASK_FMUL_S
)
501 DECLARE_INSN(csrrsi
, MATCH_CSRRSI
, MASK_CSRRSI
)
502 DECLARE_INSN(srai
, MATCH_SRAI
, MASK_SRAI
)
503 DECLARE_INSN(amoand_d
, MATCH_AMOAND_D
, MASK_AMOAND_D
)
504 DECLARE_INSN(flt_d
, MATCH_FLT_D
, MASK_FLT_D
)
505 DECLARE_INSN(sraw
, MATCH_SRAW
, MASK_SRAW
)
506 DECLARE_INSN(fmul_d
, MATCH_FMUL_D
, MASK_FMUL_D
)
507 DECLARE_INSN(ld
, MATCH_LD
, MASK_LD
)
508 DECLARE_INSN(ori
, MATCH_ORI
, MASK_ORI
)
509 DECLARE_INSN(csrrs
, MATCH_CSRRS
, MASK_CSRRS
)
510 DECLARE_INSN(flt_s
, MATCH_FLT_S
, MASK_FLT_S
)
511 DECLARE_INSN(addiw
, MATCH_ADDIW
, MASK_ADDIW
)
512 DECLARE_INSN(amoand_w
, MATCH_AMOAND_W
, MASK_AMOAND_W
)
513 DECLARE_INSN(feq_s
, MATCH_FEQ_S
, MASK_FEQ_S
)
514 DECLARE_INSN(fsgnjx_d
, MATCH_FSGNJX_D
, MASK_FSGNJX_D
)
515 DECLARE_INSN(sra
, MATCH_SRA
, MASK_SRA
)
516 DECLARE_INSN(bge
, MATCH_BGE
, MASK_BGE
)
517 DECLARE_INSN(sraiw
, MATCH_SRAIW
, MASK_SRAIW
)
518 DECLARE_INSN(srl
, MATCH_SRL
, MASK_SRL
)
519 DECLARE_INSN(fsub_d
, MATCH_FSUB_D
, MASK_FSUB_D
)
520 DECLARE_INSN(fsgnjx_s
, MATCH_FSGNJX_S
, MASK_FSGNJX_S
)
521 DECLARE_INSN(feq_d
, MATCH_FEQ_D
, MASK_FEQ_D
)
522 DECLARE_INSN(fcvt_d_wu
, MATCH_FCVT_D_WU
, MASK_FCVT_D_WU
)
523 DECLARE_INSN(or, MATCH_OR
, MASK_OR
)
524 DECLARE_INSN(fcvt_wu_d
, MATCH_FCVT_WU_D
, MASK_FCVT_WU_D
)
525 DECLARE_INSN(subw
, MATCH_SUBW
, MASK_SUBW
)
526 DECLARE_INSN(fmax_s
, MATCH_FMAX_S
, MASK_FMAX_S
)
527 DECLARE_INSN(amomaxu_d
, MATCH_AMOMAXU_D
, MASK_AMOMAXU_D
)
528 DECLARE_INSN(xori
, MATCH_XORI
, MASK_XORI
)
529 DECLARE_INSN(amoxor_d
, MATCH_AMOXOR_D
, MASK_AMOXOR_D
)
530 DECLARE_INSN(amomaxu_w
, MATCH_AMOMAXU_W
, MASK_AMOMAXU_W
)
531 DECLARE_INSN(fcvt_wu_s
, MATCH_FCVT_WU_S
, MASK_FCVT_WU_S
)
532 DECLARE_INSN(andi
, MATCH_ANDI
, MASK_ANDI
)
533 DECLARE_INSN(fmv_x_s
, MATCH_FMV_X_S
, MASK_FMV_X_S
)
534 DECLARE_INSN(sret
, MATCH_SRET
, MASK_SRET
)
535 DECLARE_INSN(fnmadd_s
, MATCH_FNMADD_S
, MASK_FNMADD_S
)
536 DECLARE_INSN(jal
, MATCH_JAL
, MASK_JAL
)
537 DECLARE_INSN(lwu
, MATCH_LWU
, MASK_LWU
)
538 DECLARE_INSN(fmv_x_d
, MATCH_FMV_X_D
, MASK_FMV_X_D
)
539 DECLARE_INSN(fcvt_d_s
, MATCH_FCVT_D_S
, MASK_FCVT_D_S
)
540 DECLARE_INSN(fnmadd_d
, MATCH_FNMADD_D
, MASK_FNMADD_D
)
541 DECLARE_INSN(amoadd_d
, MATCH_AMOADD_D
, MASK_AMOADD_D
)
542 DECLARE_INSN(lr_d
, MATCH_LR_D
, MASK_LR_D
)
543 DECLARE_INSN(fcvt_w_s
, MATCH_FCVT_W_S
, MASK_FCVT_W_S
)
544 DECLARE_INSN(mulhsu
, MATCH_MULHSU
, MASK_MULHSU
)
545 DECLARE_INSN(amoadd_w
, MATCH_AMOADD_W
, MASK_AMOADD_W
)
546 DECLARE_INSN(fcvt_d_lu
, MATCH_FCVT_D_LU
, MASK_FCVT_D_LU
)
547 DECLARE_INSN(lr_w
, MATCH_LR_W
, MASK_LR_W
)
548 DECLARE_INSN(fcvt_w_d
, MATCH_FCVT_W_D
, MASK_FCVT_W_D
)
549 DECLARE_INSN(slt
, MATCH_SLT
, MASK_SLT
)
550 DECLARE_INSN(sllw
, MATCH_SLLW
, MASK_SLLW
)
551 DECLARE_INSN(amoor_d
, MATCH_AMOOR_D
, MASK_AMOOR_D
)
552 DECLARE_INSN(slti
, MATCH_SLTI
, MASK_SLTI
)
553 DECLARE_INSN(remu
, MATCH_REMU
, MASK_REMU
)
554 DECLARE_INSN(flw
, MATCH_FLW
, MASK_FLW
)
555 DECLARE_INSN(remw
, MATCH_REMW
, MASK_REMW
)
556 DECLARE_INSN(sltu
, MATCH_SLTU
, MASK_SLTU
)
557 DECLARE_INSN(slli
, MATCH_SLLI
, MASK_SLLI
)
558 DECLARE_INSN(amoor_w
, MATCH_AMOOR_W
, MASK_AMOOR_W
)
559 DECLARE_INSN(beq
, MATCH_BEQ
, MASK_BEQ
)
560 DECLARE_INSN(fld
, MATCH_FLD
, MASK_FLD
)
561 DECLARE_INSN(fsub_s
, MATCH_FSUB_S
, MASK_FSUB_S
)
562 DECLARE_INSN(and, MATCH_AND
, MASK_AND
)
563 DECLARE_INSN(fmv_d_x
, MATCH_FMV_D_X
, MASK_FMV_D_X
)
564 DECLARE_INSN(lbu
, MATCH_LBU
, MASK_LBU
)
565 DECLARE_INSN(fsgnj_s
, MATCH_FSGNJ_S
, MASK_FSGNJ_S
)
566 DECLARE_INSN(amomax_w
, MATCH_AMOMAX_W
, MASK_AMOMAX_W
)
567 DECLARE_INSN(fsgnj_d
, MATCH_FSGNJ_D
, MASK_FSGNJ_D
)
568 DECLARE_INSN(mulhu
, MATCH_MULHU
, MASK_MULHU
)
569 DECLARE_INSN(fcvt_l_d
, MATCH_FCVT_L_D
, MASK_FCVT_L_D
)
570 DECLARE_INSN(fcvt_s_wu
, MATCH_FCVT_S_WU
, MASK_FCVT_S_WU
)
571 DECLARE_INSN(fcvt_lu_s
, MATCH_FCVT_LU_S
, MASK_FCVT_LU_S
)
572 DECLARE_INSN(fcvt_s_l
, MATCH_FCVT_S_L
, MASK_FCVT_S_L
)
573 DECLARE_INSN(auipc
, MATCH_AUIPC
, MASK_AUIPC
)
574 DECLARE_INSN(fcvt_lu_d
, MATCH_FCVT_LU_D
, MASK_FCVT_LU_D
)
575 DECLARE_INSN(csrrwi
, MATCH_CSRRWI
, MASK_CSRRWI
)
576 DECLARE_INSN(sc_d
, MATCH_SC_D
, MASK_SC_D
)
577 DECLARE_INSN(fmadd_s
, MATCH_FMADD_S
, MASK_FMADD_S
)
578 DECLARE_INSN(fsqrt_s
, MATCH_FSQRT_S
, MASK_FSQRT_S
)
579 DECLARE_INSN(amomin_w
, MATCH_AMOMIN_W
, MASK_AMOMIN_W
)
580 DECLARE_INSN(fsgnjn_s
, MATCH_FSGNJN_S
, MASK_FSGNJN_S
)
581 DECLARE_INSN(amoswap_d
, MATCH_AMOSWAP_D
, MASK_AMOSWAP_D
)
582 DECLARE_INSN(fsqrt_d
, MATCH_FSQRT_D
, MASK_FSQRT_D
)
583 DECLARE_INSN(fmadd_d
, MATCH_FMADD_D
, MASK_FMADD_D
)
584 DECLARE_INSN(divw
, MATCH_DIVW
, MASK_DIVW
)
585 DECLARE_INSN(amomin_d
, MATCH_AMOMIN_D
, MASK_AMOMIN_D
)
586 DECLARE_INSN(divu
, MATCH_DIVU
, MASK_DIVU
)
587 DECLARE_INSN(amoswap_w
, MATCH_AMOSWAP_W
, MASK_AMOSWAP_W
)
588 DECLARE_INSN(jalr
, MATCH_JALR
, MASK_JALR
)
589 DECLARE_INSN(fsd
, MATCH_FSD
, MASK_FSD
)
590 DECLARE_INSN(sw
, MATCH_SW
, MASK_SW
)
591 DECLARE_INSN(fmsub_s
, MATCH_FMSUB_S
, MASK_FMSUB_S
)
592 DECLARE_INSN(lhu
, MATCH_LHU
, MASK_LHU
)
593 DECLARE_INSN(sh
, MATCH_SH
, MASK_SH
)
594 DECLARE_INSN(fsw
, MATCH_FSW
, MASK_FSW
)
595 DECLARE_INSN(sb
, MATCH_SB
, MASK_SB
)
596 DECLARE_INSN(fmsub_d
, MATCH_FMSUB_D
, MASK_FMSUB_D
)
597 DECLARE_INSN(sd
, MATCH_SD
, MASK_SD
)
600 DECLARE_CSR(fflags
, CSR_FFLAGS
)
601 DECLARE_CSR(frm
, CSR_FRM
)
602 DECLARE_CSR(fcsr
, CSR_FCSR
)
603 DECLARE_CSR(sup0
, CSR_SUP0
)
604 DECLARE_CSR(sup1
, CSR_SUP1
)
605 DECLARE_CSR(epc
, CSR_EPC
)
606 DECLARE_CSR(badvaddr
, CSR_BADVADDR
)
607 DECLARE_CSR(ptbr
, CSR_PTBR
)
608 DECLARE_CSR(asid
, CSR_ASID
)
609 DECLARE_CSR(count
, CSR_COUNT
)
610 DECLARE_CSR(compare
, CSR_COMPARE
)
611 DECLARE_CSR(evec
, CSR_EVEC
)
612 DECLARE_CSR(cause
, CSR_CAUSE
)
613 DECLARE_CSR(status
, CSR_STATUS
)
614 DECLARE_CSR(hartid
, CSR_HARTID
)
615 DECLARE_CSR(impl
, CSR_IMPL
)
616 DECLARE_CSR(fatc
, CSR_FATC
)
617 DECLARE_CSR(send_ipi
, CSR_SEND_IPI
)
618 DECLARE_CSR(clear_ipi
, CSR_CLEAR_IPI
)
619 DECLARE_CSR(stats
, CSR_STATS
)
620 DECLARE_CSR(reset
, CSR_RESET
)
621 DECLARE_CSR(tohost
, CSR_TOHOST
)
622 DECLARE_CSR(fromhost
, CSR_FROMHOST
)
623 DECLARE_CSR(cycle
, CSR_CYCLE
)
624 DECLARE_CSR(time
, CSR_TIME
)
625 DECLARE_CSR(instret
, CSR_INSTRET
)