riscv/encoding.h

   1 // See LICENSE for license details.
   2
   3 #ifndef RISCV_CSR_ENCODING_H
   4 #define RISCV_CSR_ENCODING_H
   5
   6 #define MSTATUS_SSIP        0x00000002
   7 #define MSTATUS_HSIP        0x00000004
   8 #define MSTATUS_MSIP        0x00000008
   9 #define MSTATUS_IE          0x00000010
  10 #define MSTATUS_PRV         0x00000060
  11 #define MSTATUS_IE1         0x00000080
  12 #define MSTATUS_PRV1        0x00000300
  13 #define MSTATUS_IE2         0x00000400
  14 #define MSTATUS_PRV2        0x00001800
  15 #define MSTATUS_IE3         0x00002000
  16 #define MSTATUS_PRV3        0x0000C000
  17 #define MSTATUS_MPRV        0x00030000
  18 #define MSTATUS_VM          0x00780000
  19 #define MSTATUS_STIE        0x01000000
  20 #define MSTATUS_HTIE        0x02000000
  21 #define MSTATUS_MTIE        0x04000000
  22 #define MSTATUS_FS          0x18000000
  23 #define MSTATUS_XS          0x60000000
  24 #define MSTATUS32_SD        0x80000000
  25 #define MSTATUS64_UA        0x0000000F00000000
  26 #define MSTATUS64_SA        0x000000F000000000
  27 #define MSTATUS64_HA        0x00000F0000000000
  28 #define MSTATUS64_SD        0x8000000000000000
  29
  30 #define SSTATUS_SIP         0x00000002
  31 #define SSTATUS_IE          0x00000010
  32 #define SSTATUS_PIE         0x00000080
  33 #define SSTATUS_PS          0x00000100
  34 #define SSTATUS_UA          0x000F0000
  35 #define SSTATUS_TIE         0x01000000
  36 #define SSTATUS_TIP         0x04000000
  37 #define SSTATUS_FS          0x18000000
  38 #define SSTATUS_XS          0x60000000
  39 #define SSTATUS32_SD        0x80000000
  40 #define SSTATUS64_SD        0x8000000000000000
  41
  42 #define PRV_U 0
  43 #define PRV_S 1
  44 #define PRV_H 2
  45 #define PRV_M 3
  46
  47 #define VM_MBARE 0
  48 #define VM_MBB   1
  49 #define VM_MBBID 2
  50 #define VM_SV32  4
  51 #define VM_SV43  5
  52
  53 #define UA_RV32  0
  54 #define UA_RV64  4
  55 #define UA_RV128 8
  56
  57 #define IRQ_TIMER  0
  58 #define IRQ_IPI    1
  59 #define IRQ_HOST   2
  60 #define IRQ_COP    3
  61
  62 #define IMPL_SPIKE  1
  63 #define IMPL_ROCKET 2
  64
  65 // page table entry (PTE) fields
  66 #define PTE_V    0x001 // Entry is a page Table descriptor
  67 #define PTE_T    0x002 // Entry is a page Table, not a terminal node
  68 #define PTE_G    0x004 // Global
  69 #define PTE_UR   0x008 // User Write permission
  70 #define PTE_UW   0x010 // User Read permission
  71 #define PTE_UX   0x020 // User eXecute permission
  72 #define PTE_SR   0x040 // Supervisor Read permission
  73 #define PTE_SW   0x080 // Supervisor Write permission
  74 #define PTE_SX   0x100 // Supervisor eXecute permission
  75 #define PTE_R    0x200 // Referenced
  76 #define PTE_D    0x400 // Dirty
  77 #define PTE_PERM (PTE_SR | PTE_SW | PTE_SX | PTE_UR | PTE_UW | PTE_UX)
  78
  79 #ifdef __riscv
  80
  81 #ifdef __riscv64
  82 # define MSTATUS_UA MSTATUS64_UA
  83 # define MSTATUS_SA MSTATUS64_SA
  84 # define MSTATUS_HA MSTATUS64_HA
  85 # define MSTATUS_SD MSTATUS64_SD
  86 # define SSTATUS_SD SSTATUS64_SD
  87 # define RISCV_PGLEVELS 3
  88 # define RISCV_PGSHIFT 13
  89 #else
  90 # define MSTATUS_SD MSTATUS32_SD
  91 # define SSTATUS_SD SSTATUS32_SD
  92 # define RISCV_PGLEVELS 2
  93 # define RISCV_PGSHIFT 12
  94 #endif
  95 #define RISCV_PGLEVEL_BITS 10
  96 #define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
  97
  98 #ifndef __ASSEMBLER__
  99
 100 #ifdef __GNUC__
 101
 102 #define read_csr(reg) ({ unsigned long __tmp; \
 103   asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
 104   __tmp; })
 105
 106 #define write_csr(reg, val) \
 107   asm volatile ("csrw " #reg ", %0" :: "r"(val))
 108
 109 #define swap_csr(reg, val) ({ long __tmp; \
 110   asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
 111   __tmp; })
 112
 113 #define set_csr(reg, bit) ({ unsigned long __tmp; \
 114   if (__builtin_constant_p(bit) && (bit) < 32) \
 115     asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
 116   else \
 117     asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
 118   __tmp; })
 119
 120 #define clear_csr(reg, bit) ({ unsigned long __tmp; \
 121   if (__builtin_constant_p(bit) && (bit) < 32) \
 122     asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
 123   else \
 124     asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
 125   __tmp; })
 126
 127 #define rdtime() read_csr(time)
 128 #define rdcycle() read_csr(cycle)
 129 #define rdinstret() read_csr(instret)
 130
 131 #endif
 132
 133 #endif
 134
 135 #endif
 136
 137 #endif
 138 /* Automatically generated by parse-opcodes */
 139 #ifndef RISCV_ENCODING_H
 140 #define RISCV_ENCODING_H
 141 #define MATCH_FMV_S_X 0xf0000053
 142 #define MASK_FMV_S_X  0xfff0707f
 143 #define MATCH_AMOXOR_W 0x2000202f
 144 #define MASK_AMOXOR_W  0xf800707f
 145 #define MATCH_REMUW 0x200703b
 146 #define MASK_REMUW  0xfe00707f
 147 #define MATCH_FMIN_D 0x2a000053
 148 #define MASK_FMIN_D  0xfe00707f
 149 #define MATCH_AMOMAX_D 0xa000302f
 150 #define MASK_AMOMAX_D  0xf800707f
 151 #define MATCH_BLTU 0x6063
 152 #define MASK_BLTU  0x707f
 153 #define MATCH_FSGNJN_D 0x22001053
 154 #define MASK_FSGNJN_D  0xfe00707f
 155 #define MATCH_FMIN_S 0x28000053
 156 #define MASK_FMIN_S  0xfe00707f
 157 #define MATCH_CSRRW 0x1073
 158 #define MASK_CSRRW  0x707f
 159 #define MATCH_SLLIW 0x101b
 160 #define MASK_SLLIW  0xfe00707f
 161 #define MATCH_LB 0x3
 162 #define MASK_LB  0x707f
 163 #define MATCH_FMAX_S 0x28001053
 164 #define MASK_FMAX_S  0xfe00707f
 165 #define MATCH_LH 0x1003
 166 #define MASK_LH  0x707f
 167 #define MATCH_FCVT_D_W 0xd2000053
 168 #define MASK_FCVT_D_W  0xfff0007f
 169 #define MATCH_LW 0x2003
 170 #define MASK_LW  0x707f
 171 #define MATCH_ADD 0x33
 172 #define MASK_ADD  0xfe00707f
 173 #define MATCH_CSRRC 0x3073
 174 #define MASK_CSRRC  0x707f
 175 #define MATCH_FMAX_D 0x2a001053
 176 #define MASK_FMAX_D  0xfe00707f
 177 #define MATCH_BNE 0x1063
 178 #define MASK_BNE  0x707f
 179 #define MATCH_FCVT_S_D 0x40100053
 180 #define MASK_FCVT_S_D  0xfff0007f
 181 #define MATCH_BGEU 0x7063
 182 #define MASK_BGEU  0x707f
 183 #define MATCH_FADD_D 0x2000053
 184 #define MASK_FADD_D  0xfe00007f
 185 #define MATCH_SLTIU 0x3013
 186 #define MASK_SLTIU  0x707f
 187 #define MATCH_FADD_S 0x53
 188 #define MASK_FADD_S  0xfe00007f
 189 #define MATCH_FCLASS_D 0xe2001053
 190 #define MASK_FCLASS_D  0xfff0707f
 191 #define MATCH_FCVT_S_W 0xd0000053
 192 #define MASK_FCVT_S_W  0xfff0007f
 193 #define MATCH_MUL 0x2000033
 194 #define MASK_MUL  0xfe00707f
 195 #define MATCH_AMOMINU_D 0xc000302f
 196 #define MASK_AMOMINU_D  0xf800707f
 197 #define MATCH_FCVT_S_LU 0xd0300053
 198 #define MASK_FCVT_S_LU  0xfff0007f
 199 #define MATCH_SRLI 0x5013
 200 #define MASK_SRLI  0xfc00707f
 201 #define MATCH_AMOMINU_W 0xc000202f
 202 #define MASK_AMOMINU_W  0xf800707f
 203 #define MATCH_DIVUW 0x200503b
 204 #define MASK_DIVUW  0xfe00707f
 205 #define MATCH_MULW 0x200003b
 206 #define MASK_MULW  0xfe00707f
 207 #define MATCH_SRLW 0x503b
 208 #define MASK_SRLW  0xfe00707f
 209 #define MATCH_DIV 0x2004033
 210 #define MASK_DIV  0xfe00707f
 211 #define MATCH_FDIV_D 0x1a000053
 212 #define MASK_FDIV_D  0xfe00007f
 213 #define MATCH_FENCE 0xf
 214 #define MASK_FENCE  0x707f
 215 #define MATCH_FNMSUB_S 0x4b
 216 #define MASK_FNMSUB_S  0x600007f
 217 #define MATCH_FCVT_L_S 0xc0200053
 218 #define MASK_FCVT_L_S  0xfff0007f
 219 #define MATCH_SBREAK 0x100073
 220 #define MASK_SBREAK  0xffffffff
 221 #define MATCH_FLE_S 0xa0000053
 222 #define MASK_FLE_S  0xfe00707f
 223 #define MATCH_FDIV_S 0x18000053
 224 #define MASK_FDIV_S  0xfe00007f
 225 #define MATCH_FLE_D 0xa2000053
 226 #define MASK_FLE_D  0xfe00707f
 227 #define MATCH_FENCE_I 0x100f
 228 #define MASK_FENCE_I  0x707f
 229 #define MATCH_FNMSUB_D 0x200004b
 230 #define MASK_FNMSUB_D  0x600007f
 231 #define MATCH_ADDW 0x3b
 232 #define MASK_ADDW  0xfe00707f
 233 #define MATCH_SLL 0x1033
 234 #define MASK_SLL  0xfe00707f
 235 #define MATCH_XOR 0x4033
 236 #define MASK_XOR  0xfe00707f
 237 #define MATCH_SUB 0x40000033
 238 #define MASK_SUB  0xfe00707f
 239 #define MATCH_BLT 0x4063
 240 #define MASK_BLT  0x707f
 241 #define MATCH_SCALL 0x73
 242 #define MASK_SCALL  0xffffffff
 243 #define MATCH_FCLASS_S 0xe0001053
 244 #define MASK_FCLASS_S  0xfff0707f
 245 #define MATCH_SFENCE_VM 0x10100073
 246 #define MASK_SFENCE_VM  0xfff07fff
 247 #define MATCH_SC_W 0x1800202f
 248 #define MASK_SC_W  0xf800707f
 249 #define MATCH_REM 0x2006033
 250 #define MASK_REM  0xfe00707f
 251 #define MATCH_SRLIW 0x501b
 252 #define MASK_SRLIW  0xfe00707f
 253 #define MATCH_LUI 0x37
 254 #define MASK_LUI  0x7f
 255 #define MATCH_CSRRCI 0x7073
 256 #define MASK_CSRRCI  0x707f
 257 #define MATCH_ADDI 0x13
 258 #define MASK_ADDI  0x707f
 259 #define MATCH_MULH 0x2001033
 260 #define MASK_MULH  0xfe00707f
 261 #define MATCH_FMUL_S 0x10000053
 262 #define MASK_FMUL_S  0xfe00007f
 263 #define MATCH_CSRRSI 0x6073
 264 #define MASK_CSRRSI  0x707f
 265 #define MATCH_SRAI 0x40005013
 266 #define MASK_SRAI  0xfc00707f
 267 #define MATCH_AMOAND_D 0x6000302f
 268 #define MASK_AMOAND_D  0xf800707f
 269 #define MATCH_FLT_D 0xa2001053
 270 #define MASK_FLT_D  0xfe00707f
 271 #define MATCH_SRAW 0x4000503b
 272 #define MASK_SRAW  0xfe00707f
 273 #define MATCH_FMUL_D 0x12000053
 274 #define MASK_FMUL_D  0xfe00007f
 275 #define MATCH_LD 0x3003
 276 #define MASK_LD  0x707f
 277 #define MATCH_ORI 0x6013
 278 #define MASK_ORI  0x707f
 279 #define MATCH_CSRRS 0x2073
 280 #define MASK_CSRRS  0x707f
 281 #define MATCH_FLT_S 0xa0001053
 282 #define MASK_FLT_S  0xfe00707f
 283 #define MATCH_ADDIW 0x1b
 284 #define MASK_ADDIW  0x707f
 285 #define MATCH_AMOAND_W 0x6000202f
 286 #define MASK_AMOAND_W  0xf800707f
 287 #define MATCH_FEQ_S 0xa0002053
 288 #define MASK_FEQ_S  0xfe00707f
 289 #define MATCH_FSGNJX_D 0x22002053
 290 #define MASK_FSGNJX_D  0xfe00707f
 291 #define MATCH_SRA 0x40005033
 292 #define MASK_SRA  0xfe00707f
 293 #define MATCH_BGE 0x5063
 294 #define MASK_BGE  0x707f
 295 #define MATCH_SRAIW 0x4000501b
 296 #define MASK_SRAIW  0xfe00707f
 297 #define MATCH_SRL 0x5033
 298 #define MASK_SRL  0xfe00707f
 299 #define MATCH_FSUB_D 0xa000053
 300 #define MASK_FSUB_D  0xfe00007f
 301 #define MATCH_FSGNJX_S 0x20002053
 302 #define MASK_FSGNJX_S  0xfe00707f
 303 #define MATCH_MRTS 0x30500073
 304 #define MASK_MRTS  0xffffffff
 305 #define MATCH_FEQ_D 0xa2002053
 306 #define MASK_FEQ_D  0xfe00707f
 307 #define MATCH_FCVT_D_WU 0xd2100053
 308 #define MASK_FCVT_D_WU  0xfff0007f
 309 #define MATCH_OR 0x6033
 310 #define MASK_OR  0xfe00707f
 311 #define MATCH_FCVT_WU_D 0xc2100053
 312 #define MASK_FCVT_WU_D  0xfff0007f
 313 #define MATCH_SUBW 0x4000003b
 314 #define MASK_SUBW  0xfe00707f
 315 #define MATCH_FCVT_D_L 0xd2200053
 316 #define MASK_FCVT_D_L  0xfff0007f
 317 #define MATCH_AMOMAXU_D 0xe000302f
 318 #define MASK_AMOMAXU_D  0xf800707f
 319 #define MATCH_XORI 0x4013
 320 #define MASK_XORI  0x707f
 321 #define MATCH_AMOXOR_D 0x2000302f
 322 #define MASK_AMOXOR_D  0xf800707f
 323 #define MATCH_AMOMAXU_W 0xe000202f
 324 #define MASK_AMOMAXU_W  0xf800707f
 325 #define MATCH_FCVT_WU_S 0xc0100053
 326 #define MASK_FCVT_WU_S  0xfff0007f
 327 #define MATCH_ANDI 0x7013
 328 #define MASK_ANDI  0x707f
 329 #define MATCH_FMV_X_S 0xe0000053
 330 #define MASK_FMV_X_S  0xfff0707f
 331 #define MATCH_SRET 0x10000073
 332 #define MASK_SRET  0xffffffff
 333 #define MATCH_FNMADD_S 0x4f
 334 #define MASK_FNMADD_S  0x600007f
 335 #define MATCH_JAL 0x6f
 336 #define MASK_JAL  0x7f
 337 #define MATCH_LWU 0x6003
 338 #define MASK_LWU  0x707f
 339 #define MATCH_FMV_X_D 0xe2000053
 340 #define MASK_FMV_X_D  0xfff0707f
 341 #define MATCH_FCVT_D_S 0x42000053
 342 #define MASK_FCVT_D_S  0xfff0007f
 343 #define MATCH_FNMADD_D 0x200004f
 344 #define MASK_FNMADD_D  0x600007f
 345 #define MATCH_AMOADD_D 0x302f
 346 #define MASK_AMOADD_D  0xf800707f
 347 #define MATCH_LR_D 0x1000302f
 348 #define MASK_LR_D  0xf9f0707f
 349 #define MATCH_FCVT_W_S 0xc0000053
 350 #define MASK_FCVT_W_S  0xfff0007f
 351 #define MATCH_MULHSU 0x2002033
 352 #define MASK_MULHSU  0xfe00707f
 353 #define MATCH_AMOADD_W 0x202f
 354 #define MASK_AMOADD_W  0xf800707f
 355 #define MATCH_FCVT_D_LU 0xd2300053
 356 #define MASK_FCVT_D_LU  0xfff0007f
 357 #define MATCH_LR_W 0x1000202f
 358 #define MASK_LR_W  0xf9f0707f
 359 #define MATCH_FCVT_W_D 0xc2000053
 360 #define MASK_FCVT_W_D  0xfff0007f
 361 #define MATCH_SLT 0x2033
 362 #define MASK_SLT  0xfe00707f
 363 #define MATCH_SLLW 0x103b
 364 #define MASK_SLLW  0xfe00707f
 365 #define MATCH_AMOOR_D 0x4000302f
 366 #define MASK_AMOOR_D  0xf800707f
 367 #define MATCH_SLTI 0x2013
 368 #define MASK_SLTI  0x707f
 369 #define MATCH_REMU 0x2007033
 370 #define MASK_REMU  0xfe00707f
 371 #define MATCH_FLW 0x2007
 372 #define MASK_FLW  0x707f
 373 #define MATCH_REMW 0x200603b
 374 #define MASK_REMW  0xfe00707f
 375 #define MATCH_SLTU 0x3033
 376 #define MASK_SLTU  0xfe00707f
 377 #define MATCH_SLLI 0x1013
 378 #define MASK_SLLI  0xfc00707f
 379 #define MATCH_AMOOR_W 0x4000202f
 380 #define MASK_AMOOR_W  0xf800707f
 381 #define MATCH_BEQ 0x63
 382 #define MASK_BEQ  0x707f
 383 #define MATCH_FLD 0x3007
 384 #define MASK_FLD  0x707f
 385 #define MATCH_FSUB_S 0x8000053
 386 #define MASK_FSUB_S  0xfe00007f
 387 #define MATCH_AND 0x7033
 388 #define MASK_AND  0xfe00707f
 389 #define MATCH_FMV_D_X 0xf2000053
 390 #define MASK_FMV_D_X  0xfff0707f
 391 #define MATCH_LBU 0x4003
 392 #define MASK_LBU  0x707f
 393 #define MATCH_FSGNJ_S 0x20000053
 394 #define MASK_FSGNJ_S  0xfe00707f
 395 #define MATCH_AMOMAX_W 0xa000202f
 396 #define MASK_AMOMAX_W  0xf800707f
 397 #define MATCH_FSGNJ_D 0x22000053
 398 #define MASK_FSGNJ_D  0xfe00707f
 399 #define MATCH_MULHU 0x2003033
 400 #define MASK_MULHU  0xfe00707f
 401 #define MATCH_FCVT_L_D 0xc2200053
 402 #define MASK_FCVT_L_D  0xfff0007f
 403 #define MATCH_FCVT_S_WU 0xd0100053
 404 #define MASK_FCVT_S_WU  0xfff0007f
 405 #define MATCH_FCVT_LU_S 0xc0300053
 406 #define MASK_FCVT_LU_S  0xfff0007f
 407 #define MATCH_FCVT_S_L 0xd0200053
 408 #define MASK_FCVT_S_L  0xfff0007f
 409 #define MATCH_AUIPC 0x17
 410 #define MASK_AUIPC  0x7f
 411 #define MATCH_FCVT_LU_D 0xc2300053
 412 #define MASK_FCVT_LU_D  0xfff0007f
 413 #define MATCH_CSRRWI 0x5073
 414 #define MASK_CSRRWI  0x707f
 415 #define MATCH_SC_D 0x1800302f
 416 #define MASK_SC_D  0xf800707f
 417 #define MATCH_FMADD_S 0x43
 418 #define MASK_FMADD_S  0x600007f
 419 #define MATCH_FSQRT_S 0x58000053
 420 #define MASK_FSQRT_S  0xfff0007f
 421 #define MATCH_AMOMIN_W 0x8000202f
 422 #define MASK_AMOMIN_W  0xf800707f
 423 #define MATCH_FSGNJN_S 0x20001053
 424 #define MASK_FSGNJN_S  0xfe00707f
 425 #define MATCH_AMOSWAP_D 0x800302f
 426 #define MASK_AMOSWAP_D  0xf800707f
 427 #define MATCH_FSQRT_D 0x5a000053
 428 #define MASK_FSQRT_D  0xfff0007f
 429 #define MATCH_FMADD_D 0x2000043
 430 #define MASK_FMADD_D  0x600007f
 431 #define MATCH_DIVW 0x200403b
 432 #define MASK_DIVW  0xfe00707f
 433 #define MATCH_AMOMIN_D 0x8000302f
 434 #define MASK_AMOMIN_D  0xf800707f
 435 #define MATCH_DIVU 0x2005033
 436 #define MASK_DIVU  0xfe00707f
 437 #define MATCH_AMOSWAP_W 0x800202f
 438 #define MASK_AMOSWAP_W  0xf800707f
 439 #define MATCH_JALR 0x67
 440 #define MASK_JALR  0x707f
 441 #define MATCH_FSD 0x3027
 442 #define MASK_FSD  0x707f
 443 #define MATCH_SW 0x2023
 444 #define MASK_SW  0x707f
 445 #define MATCH_FMSUB_S 0x47
 446 #define MASK_FMSUB_S  0x600007f
 447 #define MATCH_LHU 0x5003
 448 #define MASK_LHU  0x707f
 449 #define MATCH_SH 0x1023
 450 #define MASK_SH  0x707f
 451 #define MATCH_FSW 0x2027
 452 #define MASK_FSW  0x707f
 453 #define MATCH_SB 0x23
 454 #define MASK_SB  0x707f
 455 #define MATCH_FMSUB_D 0x2000047
 456 #define MASK_FMSUB_D  0x600007f
 457 #define MATCH_SD 0x3023
 458 #define MASK_SD  0x707f
 459 #define CSR_FFLAGS 0x1
 460 #define CSR_FRM 0x2
 461 #define CSR_FCSR 0x3
 462 #define CSR_CYCLE 0xc00
 463 #define CSR_TIME 0xc01
 464 #define CSR_INSTRET 0xc02
 465 #define CSR_STATS 0xc0
 466 #define CSR_UARCH0 0xcc0
 467 #define CSR_UARCH1 0xcc1
 468 #define CSR_UARCH2 0xcc2
 469 #define CSR_UARCH3 0xcc3
 470 #define CSR_UARCH4 0xcc4
 471 #define CSR_UARCH5 0xcc5
 472 #define CSR_UARCH6 0xcc6
 473 #define CSR_UARCH7 0xcc7
 474 #define CSR_UARCH8 0xcc8
 475 #define CSR_UARCH9 0xcc9
 476 #define CSR_UARCH10 0xcca
 477 #define CSR_UARCH11 0xccb
 478 #define CSR_UARCH12 0xccc
 479 #define CSR_UARCH13 0xccd
 480 #define CSR_UARCH14 0xcce
 481 #define CSR_UARCH15 0xccf
 482 #define CSR_SSTATUS 0x100
 483 #define CSR_STVEC 0x101
 484 #define CSR_STIMECMP 0x121
 485 #define CSR_SSCRATCH 0x140
 486 #define CSR_SEPC 0x141
 487 #define CSR_SPTBR 0x188
 488 #define CSR_SASID 0x189
 489 #define CSR_SCYCLE 0x900
 490 #define CSR_STIME 0x901
 491 #define CSR_SINSTRET 0x902
 492 #define CSR_SCAUSE 0xd40
 493 #define CSR_SBADADDR 0xd41
 494 #define CSR_MSTATUS 0x300
 495 #define CSR_MSCRATCH 0x340
 496 #define CSR_MEPC 0x341
 497 #define CSR_MCAUSE 0x342
 498 #define CSR_MBADADDR 0x343
 499 #define CSR_RESET 0x780
 500 #define CSR_TOHOST 0x781
 501 #define CSR_FROMHOST 0x782
 502 #define CSR_SEND_IPI 0x783
 503 #define CSR_HARTID 0xfc0
 504 #define CSR_CYCLEH 0xc80
 505 #define CSR_TIMEH 0xc81
 506 #define CSR_INSTRETH 0xc82
 507 #define CSR_SCYCLEH 0x980
 508 #define CSR_STIMEH 0x981
 509 #define CSR_SINSTRETH 0x982
 510 #define CAUSE_MISALIGNED_FETCH 0x0
 511 #define CAUSE_FAULT_FETCH 0x1
 512 #define CAUSE_ILLEGAL_INSTRUCTION 0x2
 513 #define CAUSE_MISALIGNED_LOAD 0x4
 514 #define CAUSE_FAULT_LOAD 0x5
 515 #define CAUSE_MISALIGNED_STORE 0x6
 516 #define CAUSE_FAULT_STORE 0x7
 517 #define CAUSE_ECALL 0x8
 518 #define CAUSE_BREAKPOINT 0x9
 519 #endif
 520 #ifdef DECLARE_INSN
 521 DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
 522 DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
 523 DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
 524 DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
 525 DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
 526 DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
 527 DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
 528 DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
 529 DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
 530 DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
 531 DECLARE_INSN(lb, MATCH_LB, MASK_LB)
 532 DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
 533 DECLARE_INSN(lh, MATCH_LH, MASK_LH)
 534 DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
 535 DECLARE_INSN(lw, MATCH_LW, MASK_LW)
 536 DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
 537 DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
 538 DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
 539 DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
 540 DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
 541 DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
 542 DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
 543 DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
 544 DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
 545 DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
 546 DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
 547 DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
 548 DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
 549 DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
 550 DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
 551 DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
 552 DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
 553 DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
 554 DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
 555 DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
 556 DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
 557 DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
 558 DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
 559 DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
 560 DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK)
 561 DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
 562 DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
 563 DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
 564 DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
 565 DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
 566 DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
 567 DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
 568 DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
 569 DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
 570 DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
 571 DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL)
 572 DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
 573 DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
 574 DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
 575 DECLARE_INSN(rem, MATCH_REM, MASK_REM)
 576 DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
 577 DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
 578 DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
 579 DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
 580 DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
 581 DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
 582 DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
 583 DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
 584 DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
 585 DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
 586 DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
 587 DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
 588 DECLARE_INSN(ld, MATCH_LD, MASK_LD)
 589 DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
 590 DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
 591 DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
 592 DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
 593 DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
 594 DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
 595 DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
 596 DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
 597 DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
 598 DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
 599 DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
 600 DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
 601 DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
 602 DECLARE_INSN(mrts, MATCH_MRTS, MASK_MRTS)
 603 DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
 604 DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
 605 DECLARE_INSN(or, MATCH_OR, MASK_OR)
 606 DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
 607 DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
 608 DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
 609 DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
 610 DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
 611 DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
 612 DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
 613 DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
 614 DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
 615 DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
 616 DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
 617 DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
 618 DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
 619 DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
 620 DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
 621 DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
 622 DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
 623 DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
 624 DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
 625 DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
 626 DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
 627 DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
 628 DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
 629 DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
 630 DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
 631 DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
 632 DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
 633 DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
 634 DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
 635 DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
 636 DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
 637 DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
 638 DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
 639 DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
 640 DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
 641 DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
 642 DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
 643 DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
 644 DECLARE_INSN(and, MATCH_AND, MASK_AND)
 645 DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
 646 DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
 647 DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
 648 DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
 649 DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
 650 DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
 651 DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
 652 DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
 653 DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
 654 DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
 655 DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
 656 DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
 657 DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
 658 DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
 659 DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
 660 DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
 661 DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
 662 DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
 663 DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
 664 DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
 665 DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
 666 DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
 667 DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
 668 DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
 669 DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
 670 DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
 671 DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
 672 DECLARE_INSN(sw, MATCH_SW, MASK_SW)
 673 DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
 674 DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
 675 DECLARE_INSN(sh, MATCH_SH, MASK_SH)
 676 DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
 677 DECLARE_INSN(sb, MATCH_SB, MASK_SB)
 678 DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
 679 DECLARE_INSN(sd, MATCH_SD, MASK_SD)
 680 #endif
 681 #ifdef DECLARE_CSR
 682 DECLARE_CSR(fflags, CSR_FFLAGS)
 683 DECLARE_CSR(frm, CSR_FRM)
 684 DECLARE_CSR(fcsr, CSR_FCSR)
 685 DECLARE_CSR(cycle, CSR_CYCLE)
 686 DECLARE_CSR(time, CSR_TIME)
 687 DECLARE_CSR(instret, CSR_INSTRET)
 688 DECLARE_CSR(stats, CSR_STATS)
 689 DECLARE_CSR(uarch0, CSR_UARCH0)
 690 DECLARE_CSR(uarch1, CSR_UARCH1)
 691 DECLARE_CSR(uarch2, CSR_UARCH2)
 692 DECLARE_CSR(uarch3, CSR_UARCH3)
 693 DECLARE_CSR(uarch4, CSR_UARCH4)
 694 DECLARE_CSR(uarch5, CSR_UARCH5)
 695 DECLARE_CSR(uarch6, CSR_UARCH6)
 696 DECLARE_CSR(uarch7, CSR_UARCH7)
 697 DECLARE_CSR(uarch8, CSR_UARCH8)
 698 DECLARE_CSR(uarch9, CSR_UARCH9)
 699 DECLARE_CSR(uarch10, CSR_UARCH10)
 700 DECLARE_CSR(uarch11, CSR_UARCH11)
 701 DECLARE_CSR(uarch12, CSR_UARCH12)
 702 DECLARE_CSR(uarch13, CSR_UARCH13)
 703 DECLARE_CSR(uarch14, CSR_UARCH14)
 704 DECLARE_CSR(uarch15, CSR_UARCH15)
 705 DECLARE_CSR(sstatus, CSR_SSTATUS)
 706 DECLARE_CSR(stvec, CSR_STVEC)
 707 DECLARE_CSR(stimecmp, CSR_STIMECMP)
 708 DECLARE_CSR(sscratch, CSR_SSCRATCH)
 709 DECLARE_CSR(sepc, CSR_SEPC)
 710 DECLARE_CSR(sptbr, CSR_SPTBR)
 711 DECLARE_CSR(sasid, CSR_SASID)
 712 DECLARE_CSR(scycle, CSR_SCYCLE)
 713 DECLARE_CSR(stime, CSR_STIME)
 714 DECLARE_CSR(sinstret, CSR_SINSTRET)
 715 DECLARE_CSR(scause, CSR_SCAUSE)
 716 DECLARE_CSR(sbadaddr, CSR_SBADADDR)
 717 DECLARE_CSR(mstatus, CSR_MSTATUS)
 718 DECLARE_CSR(mscratch, CSR_MSCRATCH)
 719 DECLARE_CSR(mepc, CSR_MEPC)
 720 DECLARE_CSR(mcause, CSR_MCAUSE)
 721 DECLARE_CSR(mbadaddr, CSR_MBADADDR)
 722 DECLARE_CSR(reset, CSR_RESET)
 723 DECLARE_CSR(tohost, CSR_TOHOST)
 724 DECLARE_CSR(fromhost, CSR_FROMHOST)
 725 DECLARE_CSR(send_ipi, CSR_SEND_IPI)
 726 DECLARE_CSR(hartid, CSR_HARTID)
 727 DECLARE_CSR(cycleh, CSR_CYCLEH)
 728 DECLARE_CSR(timeh, CSR_TIMEH)
 729 DECLARE_CSR(instreth, CSR_INSTRETH)
 730 DECLARE_CSR(scycleh, CSR_SCYCLEH)
 731 DECLARE_CSR(stimeh, CSR_STIMEH)
 732 DECLARE_CSR(sinstreth, CSR_SINSTRETH)
 733 #endif
 734 #ifdef DECLARE_CAUSE
 735 DECLARE_CAUSE("fflags", CAUSE_FFLAGS)
 736 DECLARE_CAUSE("frm", CAUSE_FRM)
 737 DECLARE_CAUSE("fcsr", CAUSE_FCSR)
 738 DECLARE_CAUSE("cycle", CAUSE_CYCLE)
 739 DECLARE_CAUSE("time", CAUSE_TIME)
 740 DECLARE_CAUSE("instret", CAUSE_INSTRET)
 741 DECLARE_CAUSE("stats", CAUSE_STATS)
 742 DECLARE_CAUSE("uarch0", CAUSE_UARCH0)
 743 DECLARE_CAUSE("uarch1", CAUSE_UARCH1)
 744 DECLARE_CAUSE("uarch2", CAUSE_UARCH2)
 745 DECLARE_CAUSE("uarch3", CAUSE_UARCH3)
 746 DECLARE_CAUSE("uarch4", CAUSE_UARCH4)
 747 DECLARE_CAUSE("uarch5", CAUSE_UARCH5)
 748 DECLARE_CAUSE("uarch6", CAUSE_UARCH6)
 749 DECLARE_CAUSE("uarch7", CAUSE_UARCH7)
 750 DECLARE_CAUSE("uarch8", CAUSE_UARCH8)
 751 DECLARE_CAUSE("uarch9", CAUSE_UARCH9)
 752 DECLARE_CAUSE("uarch10", CAUSE_UARCH10)
 753 DECLARE_CAUSE("uarch11", CAUSE_UARCH11)
 754 DECLARE_CAUSE("uarch12", CAUSE_UARCH12)
 755 DECLARE_CAUSE("uarch13", CAUSE_UARCH13)
 756 DECLARE_CAUSE("uarch14", CAUSE_UARCH14)
 757 DECLARE_CAUSE("uarch15", CAUSE_UARCH15)
 758 DECLARE_CAUSE("sstatus", CAUSE_SSTATUS)
 759 DECLARE_CAUSE("stvec", CAUSE_STVEC)
 760 DECLARE_CAUSE("stimecmp", CAUSE_STIMECMP)
 761 DECLARE_CAUSE("sscratch", CAUSE_SSCRATCH)
 762 DECLARE_CAUSE("sepc", CAUSE_SEPC)
 763 DECLARE_CAUSE("sptbr", CAUSE_SPTBR)
 764 DECLARE_CAUSE("sasid", CAUSE_SASID)
 765 DECLARE_CAUSE("scycle", CAUSE_SCYCLE)
 766 DECLARE_CAUSE("stime", CAUSE_STIME)
 767 DECLARE_CAUSE("sinstret", CAUSE_SINSTRET)
 768 DECLARE_CAUSE("scause", CAUSE_SCAUSE)
 769 DECLARE_CAUSE("sbadaddr", CAUSE_SBADADDR)
 770 DECLARE_CAUSE("mstatus", CAUSE_MSTATUS)
 771 DECLARE_CAUSE("mscratch", CAUSE_MSCRATCH)
 772 DECLARE_CAUSE("mepc", CAUSE_MEPC)
 773 DECLARE_CAUSE("mcause", CAUSE_MCAUSE)
 774 DECLARE_CAUSE("mbadaddr", CAUSE_MBADADDR)
 775 DECLARE_CAUSE("reset", CAUSE_RESET)
 776 DECLARE_CAUSE("tohost", CAUSE_TOHOST)
 777 DECLARE_CAUSE("fromhost", CAUSE_FROMHOST)
 778 DECLARE_CAUSE("send_ipi", CAUSE_SEND_IPI)
 779 DECLARE_CAUSE("hartid", CAUSE_HARTID)
 780 DECLARE_CAUSE("cycleh", CAUSE_CYCLEH)
 781 DECLARE_CAUSE("timeh", CAUSE_TIMEH)
 782 DECLARE_CAUSE("instreth", CAUSE_INSTRETH)
 783 DECLARE_CAUSE("scycleh", CAUSE_SCYCLEH)
 784 DECLARE_CAUSE("stimeh", CAUSE_STIMEH)
 785 DECLARE_CAUSE("sinstreth", CAUSE_SINSTRETH)
 786 #endif