1 // See LICENSE for license details.
3 #ifndef RISCV_CSR_ENCODING_H
4 #define RISCV_CSR_ENCODING_H
6 #define SR_S 0x00000001
7 #define SR_PS 0x00000002
8 #define SR_EI 0x00000004
9 #define SR_PEI 0x00000008
10 #define SR_EF 0x00000010
11 #define SR_U64 0x00000020
12 #define SR_S64 0x00000040
13 #define SR_VM 0x00000080
14 #define SR_EA 0x00000100
15 #define SR_IM 0x00FF0000
16 #define SR_IP 0xFF000000
17 #define SR_ZERO ~(SR_S|SR_PS|SR_EI|SR_PEI|SR_EF|SR_U64|SR_S64|SR_VM|SR_EA|SR_IM|SR_IP)
18 #define SR_IM_SHIFT 16
19 #define SR_IP_SHIFT 24
29 // page table entry (PTE) fields
30 #define PTE_V 0x001 // Entry is a page Table descriptor
31 #define PTE_T 0x002 // Entry is a page Table, not a terminal node
32 #define PTE_G 0x004 // Global
33 #define PTE_UR 0x008 // User Write permission
34 #define PTE_UW 0x010 // User Read permission
35 #define PTE_UX 0x020 // User eXecute permission
36 #define PTE_SR 0x040 // Supervisor Read permission
37 #define PTE_SW 0x080 // Supervisor Write permission
38 #define PTE_SX 0x100 // Supervisor eXecute permission
39 #define PTE_PERM (PTE_SR | PTE_SW | PTE_SX | PTE_UR | PTE_UW | PTE_UX)
44 # define RISCV_PGLEVELS 3
45 # define RISCV_PGSHIFT 13
47 # define RISCV_PGLEVELS 2
48 # define RISCV_PGSHIFT 12
50 #define RISCV_PGLEVEL_BITS 10
51 #define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
55 #define read_csr(reg) ({ long __tmp; \
56 asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
59 #define write_csr(reg, val) \
60 asm volatile ("csrw " #reg ", %0" :: "r"(val))
62 #define swap_csr(reg, val) ({ long __tmp; \
63 asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
66 #define set_csr(reg, bit) ({ long __tmp; \
67 if (__builtin_constant_p(bit) && (bit) < 32) \
68 asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
70 asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
73 #define clear_csr(reg, bit) ({ long __tmp; \
74 if (__builtin_constant_p(bit) && (bit) < 32) \
75 asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
77 asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
80 #define rdtime() ({ unsigned long __tmp; \
81 asm volatile ("rdtime %0" : "=r"(__tmp)); \
84 #define rdcycle() ({ unsigned long __tmp; \
85 asm volatile ("rdcycle %0" : "=r"(__tmp)); \
88 #define rdinstret() ({ unsigned long __tmp; \
89 asm volatile ("rdinstret %0" : "=r"(__tmp)); \
97 /* Automatically generated by parse-opcodes */
98 #ifndef RISCV_ENCODING_H
99 #define RISCV_ENCODING_H
100 #define MATCH_FMV_S_X 0xf0000053
101 #define MASK_FMV_S_X 0xfff0707f
102 #define MATCH_CUSTOM1_RS1 0x202b
103 #define MASK_CUSTOM1_RS1 0x707f
104 #define MATCH_AMOXOR_W 0x2000202f
105 #define MASK_AMOXOR_W 0xf800707f
106 #define MATCH_REMUW 0x200703b
107 #define MASK_REMUW 0xfe00707f
108 #define MATCH_FMIN_D 0x2a000053
109 #define MASK_FMIN_D 0xfe00707f
110 #define MATCH_AMOMAX_D 0xa000302f
111 #define MASK_AMOMAX_D 0xf800707f
112 #define MATCH_BLTU 0x6063
113 #define MASK_BLTU 0x707f
114 #define MATCH_FSGNJN_D 0x22001053
115 #define MASK_FSGNJN_D 0xfe00707f
116 #define MATCH_FMIN_S 0x28000053
117 #define MASK_FMIN_S 0xfe00707f
118 #define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
119 #define MASK_CUSTOM3_RD_RS1_RS2 0x707f
120 #define MATCH_CSRRW 0x1073
121 #define MASK_CSRRW 0x707f
122 #define MATCH_SLLIW 0x101b
123 #define MASK_SLLIW 0xfe00707f
125 #define MASK_LB 0x707f
126 #define MATCH_CUSTOM1_RD 0x402b
127 #define MASK_CUSTOM1_RD 0x707f
128 #define MATCH_FMAX_S 0x28001053
129 #define MASK_FMAX_S 0xfe00707f
130 #define MATCH_LH 0x1003
131 #define MASK_LH 0x707f
132 #define MATCH_FCVT_D_W 0xd2000053
133 #define MASK_FCVT_D_W 0xfff0007f
134 #define MATCH_LW 0x2003
135 #define MASK_LW 0x707f
136 #define MATCH_ADD 0x33
137 #define MASK_ADD 0xfe00707f
138 #define MATCH_CSRRC 0x3073
139 #define MASK_CSRRC 0x707f
140 #define MATCH_FMAX_D 0x2a001053
141 #define MASK_FMAX_D 0xfe00707f
142 #define MATCH_BNE 0x1063
143 #define MASK_BNE 0x707f
144 #define MATCH_FCVT_S_D 0x40100053
145 #define MASK_FCVT_S_D 0xfff0007f
146 #define MATCH_BGEU 0x7063
147 #define MASK_BGEU 0x707f
148 #define MATCH_FADD_D 0x2000053
149 #define MASK_FADD_D 0xfe00007f
150 #define MATCH_SLTIU 0x3013
151 #define MASK_SLTIU 0x707f
152 #define MATCH_FADD_S 0x53
153 #define MASK_FADD_S 0xfe00007f
154 #define MATCH_FCLASS_D 0xe2001053
155 #define MASK_FCLASS_D 0xfff0707f
156 #define MATCH_FCVT_S_W 0xd0000053
157 #define MASK_FCVT_S_W 0xfff0007f
158 #define MATCH_MUL 0x2000033
159 #define MASK_MUL 0xfe00707f
160 #define MATCH_AMOMINU_D 0xc000302f
161 #define MASK_AMOMINU_D 0xf800707f
162 #define MATCH_FCVT_S_LU 0xd0300053
163 #define MASK_FCVT_S_LU 0xfff0007f
164 #define MATCH_SRLI 0x5013
165 #define MASK_SRLI 0xfc00707f
166 #define MATCH_AMOMINU_W 0xc000202f
167 #define MASK_AMOMINU_W 0xf800707f
168 #define MATCH_DIVUW 0x200503b
169 #define MASK_DIVUW 0xfe00707f
170 #define MATCH_MULW 0x200003b
171 #define MASK_MULW 0xfe00707f
172 #define MATCH_SRLW 0x503b
173 #define MASK_SRLW 0xfe00707f
174 #define MATCH_DIV 0x2004033
175 #define MASK_DIV 0xfe00707f
176 #define MATCH_FDIV_D 0x1a000053
177 #define MASK_FDIV_D 0xfe00007f
178 #define MATCH_FENCE 0xf
179 #define MASK_FENCE 0x707f
180 #define MATCH_CUSTOM0_RS1_RS2 0x300b
181 #define MASK_CUSTOM0_RS1_RS2 0x707f
182 #define MATCH_FNMSUB_S 0x4b
183 #define MASK_FNMSUB_S 0x600007f
184 #define MATCH_FCVT_L_S 0xc0200053
185 #define MASK_FCVT_L_S 0xfff0007f
186 #define MATCH_SBREAK 0x100073
187 #define MASK_SBREAK 0xffffffff
188 #define MATCH_FLE_S 0xa0000053
189 #define MASK_FLE_S 0xfe00707f
190 #define MATCH_FDIV_S 0x18000053
191 #define MASK_FDIV_S 0xfe00007f
192 #define MATCH_FLE_D 0xa2000053
193 #define MASK_FLE_D 0xfe00707f
194 #define MATCH_FENCE_I 0x100f
195 #define MASK_FENCE_I 0x707f
196 #define MATCH_FNMSUB_D 0x200004b
197 #define MASK_FNMSUB_D 0x600007f
198 #define MATCH_ADDW 0x3b
199 #define MASK_ADDW 0xfe00707f
200 #define MATCH_SLL 0x1033
201 #define MASK_SLL 0xfe00707f
202 #define MATCH_XOR 0x4033
203 #define MASK_XOR 0xfe00707f
204 #define MATCH_SUB 0x40000033
205 #define MASK_SUB 0xfe00707f
206 #define MATCH_BLT 0x4063
207 #define MASK_BLT 0x707f
208 #define MATCH_SCALL 0x73
209 #define MASK_SCALL 0xffffffff
210 #define MATCH_CUSTOM2_RD_RS1 0x605b
211 #define MASK_CUSTOM2_RD_RS1 0x707f
212 #define MATCH_FCLASS_S 0xe0001053
213 #define MASK_FCLASS_S 0xfff0707f
214 #define MATCH_SC_W 0x1800202f
215 #define MASK_SC_W 0xf800707f
216 #define MATCH_REM 0x2006033
217 #define MASK_REM 0xfe00707f
218 #define MATCH_SRLIW 0x501b
219 #define MASK_SRLIW 0xfe00707f
220 #define MATCH_LUI 0x37
221 #define MASK_LUI 0x7f
222 #define MATCH_CSRRCI 0x7073
223 #define MASK_CSRRCI 0x707f
224 #define MATCH_ADDI 0x13
225 #define MASK_ADDI 0x707f
226 #define MATCH_MULH 0x2001033
227 #define MASK_MULH 0xfe00707f
228 #define MATCH_FMUL_S 0x10000053
229 #define MASK_FMUL_S 0xfe00007f
230 #define MATCH_CSRRSI 0x6073
231 #define MASK_CSRRSI 0x707f
232 #define MATCH_SRAI 0x40005013
233 #define MASK_SRAI 0xfc00707f
234 #define MATCH_AMOAND_D 0x6000302f
235 #define MASK_AMOAND_D 0xf800707f
236 #define MATCH_FLT_D 0xa2001053
237 #define MASK_FLT_D 0xfe00707f
238 #define MATCH_SRAW 0x4000503b
239 #define MASK_SRAW 0xfe00707f
240 #define MATCH_FMUL_D 0x12000053
241 #define MASK_FMUL_D 0xfe00007f
242 #define MATCH_LD 0x3003
243 #define MASK_LD 0x707f
244 #define MATCH_ORI 0x6013
245 #define MASK_ORI 0x707f
246 #define MATCH_CSRRS 0x2073
247 #define MASK_CSRRS 0x707f
248 #define MATCH_FLT_S 0xa0001053
249 #define MASK_FLT_S 0xfe00707f
250 #define MATCH_ADDIW 0x1b
251 #define MASK_ADDIW 0x707f
252 #define MATCH_AMOAND_W 0x6000202f
253 #define MASK_AMOAND_W 0xf800707f
254 #define MATCH_FEQ_S 0xa0002053
255 #define MASK_FEQ_S 0xfe00707f
256 #define MATCH_FSGNJX_D 0x22002053
257 #define MASK_FSGNJX_D 0xfe00707f
258 #define MATCH_SRA 0x40005033
259 #define MASK_SRA 0xfe00707f
260 #define MATCH_BGE 0x5063
261 #define MASK_BGE 0x707f
262 #define MATCH_SRAIW 0x4000501b
263 #define MASK_SRAIW 0xfe00707f
264 #define MATCH_SRL 0x5033
265 #define MASK_SRL 0xfe00707f
266 #define MATCH_CUSTOM3_RS1 0x207b
267 #define MASK_CUSTOM3_RS1 0x707f
268 #define MATCH_FSUB_D 0xa000053
269 #define MASK_FSUB_D 0xfe00007f
270 #define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
271 #define MASK_CUSTOM1_RD_RS1_RS2 0x707f
272 #define MATCH_FSGNJX_S 0x20002053
273 #define MASK_FSGNJX_S 0xfe00707f
274 #define MATCH_FEQ_D 0xa2002053
275 #define MASK_FEQ_D 0xfe00707f
276 #define MATCH_CUSTOM1_RD_RS1 0x602b
277 #define MASK_CUSTOM1_RD_RS1 0x707f
278 #define MATCH_FCVT_D_WU 0xd2100053
279 #define MASK_FCVT_D_WU 0xfff0007f
280 #define MATCH_OR 0x6033
281 #define MASK_OR 0xfe00707f
282 #define MATCH_FCVT_WU_D 0xc2100053
283 #define MASK_FCVT_WU_D 0xfff0007f
284 #define MATCH_SUBW 0x4000003b
285 #define MASK_SUBW 0xfe00707f
286 #define MATCH_FCVT_D_L 0xd2200053
287 #define MASK_FCVT_D_L 0xfff0007f
288 #define MATCH_AMOMAXU_D 0xe000302f
289 #define MASK_AMOMAXU_D 0xf800707f
290 #define MATCH_XORI 0x4013
291 #define MASK_XORI 0x707f
292 #define MATCH_AMOXOR_D 0x2000302f
293 #define MASK_AMOXOR_D 0xf800707f
294 #define MATCH_AMOMAXU_W 0xe000202f
295 #define MASK_AMOMAXU_W 0xf800707f
296 #define MATCH_FCVT_WU_S 0xc0100053
297 #define MASK_FCVT_WU_S 0xfff0007f
298 #define MATCH_CUSTOM3_RD 0x407b
299 #define MASK_CUSTOM3_RD 0x707f
300 #define MATCH_CUSTOM0_RS1 0x200b
301 #define MASK_CUSTOM0_RS1 0x707f
302 #define MATCH_ANDI 0x7013
303 #define MASK_ANDI 0x707f
304 #define MATCH_FMV_X_S 0xe0000053
305 #define MASK_FMV_X_S 0xfff0707f
306 #define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
307 #define MASK_CUSTOM0_RD_RS1_RS2 0x707f
308 #define MATCH_SRET 0x80000073
309 #define MASK_SRET 0xffffffff
310 #define MATCH_FNMADD_S 0x4f
311 #define MASK_FNMADD_S 0x600007f
312 #define MATCH_JAL 0x6f
313 #define MASK_JAL 0x7f
314 #define MATCH_LWU 0x6003
315 #define MASK_LWU 0x707f
316 #define MATCH_FMV_X_D 0xe2000053
317 #define MASK_FMV_X_D 0xfff0707f
318 #define MATCH_CUSTOM0_RD 0x400b
319 #define MASK_CUSTOM0_RD 0x707f
320 #define MATCH_FCVT_D_S 0x42000053
321 #define MASK_FCVT_D_S 0xfff0007f
322 #define MATCH_FNMADD_D 0x200004f
323 #define MASK_FNMADD_D 0x600007f
324 #define MATCH_AMOADD_D 0x302f
325 #define MASK_AMOADD_D 0xf800707f
326 #define MATCH_CUSTOM3_RD_RS1 0x607b
327 #define MASK_CUSTOM3_RD_RS1 0x707f
328 #define MATCH_LR_D 0x1000302f
329 #define MASK_LR_D 0xf9f0707f
330 #define MATCH_FCVT_W_S 0xc0000053
331 #define MASK_FCVT_W_S 0xfff0007f
332 #define MATCH_MULHSU 0x2002033
333 #define MASK_MULHSU 0xfe00707f
334 #define MATCH_AMOADD_W 0x202f
335 #define MASK_AMOADD_W 0xf800707f
336 #define MATCH_FCVT_D_LU 0xd2300053
337 #define MASK_FCVT_D_LU 0xfff0007f
338 #define MATCH_LR_W 0x1000202f
339 #define MASK_LR_W 0xf9f0707f
340 #define MATCH_CUSTOM3_RS1_RS2 0x307b
341 #define MASK_CUSTOM3_RS1_RS2 0x707f
342 #define MATCH_FCVT_W_D 0xc2000053
343 #define MASK_FCVT_W_D 0xfff0007f
344 #define MATCH_CUSTOM1_RS1_RS2 0x302b
345 #define MASK_CUSTOM1_RS1_RS2 0x707f
346 #define MATCH_SLT 0x2033
347 #define MASK_SLT 0xfe00707f
348 #define MATCH_SLLW 0x103b
349 #define MASK_SLLW 0xfe00707f
350 #define MATCH_AMOOR_D 0x4000302f
351 #define MASK_AMOOR_D 0xf800707f
352 #define MATCH_SLTI 0x2013
353 #define MASK_SLTI 0x707f
354 #define MATCH_REMU 0x2007033
355 #define MASK_REMU 0xfe00707f
356 #define MATCH_FLW 0x2007
357 #define MASK_FLW 0x707f
358 #define MATCH_REMW 0x200603b
359 #define MASK_REMW 0xfe00707f
360 #define MATCH_SLTU 0x3033
361 #define MASK_SLTU 0xfe00707f
362 #define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
363 #define MASK_CUSTOM2_RD_RS1_RS2 0x707f
364 #define MATCH_SLLI 0x1013
365 #define MASK_SLLI 0xfc00707f
366 #define MATCH_CUSTOM2_RD 0x405b
367 #define MASK_CUSTOM2_RD 0x707f
368 #define MATCH_AMOOR_W 0x4000202f
369 #define MASK_AMOOR_W 0xf800707f
370 #define MATCH_BEQ 0x63
371 #define MASK_BEQ 0x707f
372 #define MATCH_FLD 0x3007
373 #define MASK_FLD 0x707f
374 #define MATCH_FSUB_S 0x8000053
375 #define MASK_FSUB_S 0xfe00007f
376 #define MATCH_AND 0x7033
377 #define MASK_AND 0xfe00707f
378 #define MATCH_FMV_D_X 0xf2000053
379 #define MASK_FMV_D_X 0xfff0707f
380 #define MATCH_LBU 0x4003
381 #define MASK_LBU 0x707f
382 #define MATCH_CUSTOM2_RS1_RS2 0x305b
383 #define MASK_CUSTOM2_RS1_RS2 0x707f
384 #define MATCH_FSGNJ_S 0x20000053
385 #define MASK_FSGNJ_S 0xfe00707f
386 #define MATCH_CUSTOM0 0xb
387 #define MASK_CUSTOM0 0x707f
388 #define MATCH_CUSTOM1 0x2b
389 #define MASK_CUSTOM1 0x707f
390 #define MATCH_CUSTOM2 0x5b
391 #define MASK_CUSTOM2 0x707f
392 #define MATCH_CUSTOM3 0x7b
393 #define MASK_CUSTOM3 0x707f
394 #define MATCH_AMOMAX_W 0xa000202f
395 #define MASK_AMOMAX_W 0xf800707f
396 #define MATCH_FSGNJ_D 0x22000053
397 #define MASK_FSGNJ_D 0xfe00707f
398 #define MATCH_MULHU 0x2003033
399 #define MASK_MULHU 0xfe00707f
400 #define MATCH_FCVT_L_D 0xc2200053
401 #define MASK_FCVT_L_D 0xfff0007f
402 #define MATCH_FCVT_S_WU 0xd0100053
403 #define MASK_FCVT_S_WU 0xfff0007f
404 #define MATCH_FCVT_LU_S 0xc0300053
405 #define MASK_FCVT_LU_S 0xfff0007f
406 #define MATCH_FCVT_S_L 0xd0200053
407 #define MASK_FCVT_S_L 0xfff0007f
408 #define MATCH_CUSTOM0_RD_RS1 0x600b
409 #define MASK_CUSTOM0_RD_RS1 0x707f
410 #define MATCH_AUIPC 0x17
411 #define MASK_AUIPC 0x7f
412 #define MATCH_FCVT_LU_D 0xc2300053
413 #define MASK_FCVT_LU_D 0xfff0007f
414 #define MATCH_CSRRWI 0x5073
415 #define MASK_CSRRWI 0x707f
416 #define MATCH_SC_D 0x1800302f
417 #define MASK_SC_D 0xf800707f
418 #define MATCH_FMADD_S 0x43
419 #define MASK_FMADD_S 0x600007f
420 #define MATCH_FSQRT_S 0x58000053
421 #define MASK_FSQRT_S 0xfff0007f
422 #define MATCH_AMOMIN_W 0x8000202f
423 #define MASK_AMOMIN_W 0xf800707f
424 #define MATCH_FSGNJN_S 0x20001053
425 #define MASK_FSGNJN_S 0xfe00707f
426 #define MATCH_AMOSWAP_D 0x800302f
427 #define MASK_AMOSWAP_D 0xf800707f
428 #define MATCH_FSQRT_D 0x5a000053
429 #define MASK_FSQRT_D 0xfff0007f
430 #define MATCH_FMADD_D 0x2000043
431 #define MASK_FMADD_D 0x600007f
432 #define MATCH_DIVW 0x200403b
433 #define MASK_DIVW 0xfe00707f
434 #define MATCH_AMOMIN_D 0x8000302f
435 #define MASK_AMOMIN_D 0xf800707f
436 #define MATCH_DIVU 0x2005033
437 #define MASK_DIVU 0xfe00707f
438 #define MATCH_AMOSWAP_W 0x800202f
439 #define MASK_AMOSWAP_W 0xf800707f
440 #define MATCH_JALR 0x67
441 #define MASK_JALR 0x707f
442 #define MATCH_FSD 0x3027
443 #define MASK_FSD 0x707f
444 #define MATCH_CUSTOM2_RS1 0x205b
445 #define MASK_CUSTOM2_RS1 0x707f
446 #define MATCH_SW 0x2023
447 #define MASK_SW 0x707f
448 #define MATCH_FMSUB_S 0x47
449 #define MASK_FMSUB_S 0x600007f
450 #define MATCH_LHU 0x5003
451 #define MASK_LHU 0x707f
452 #define MATCH_SH 0x1023
453 #define MASK_SH 0x707f
454 #define MATCH_FSW 0x2027
455 #define MASK_FSW 0x707f
456 #define MATCH_SB 0x23
457 #define MASK_SB 0x707f
458 #define MATCH_FMSUB_D 0x2000047
459 #define MASK_FMSUB_D 0x600007f
460 #define MATCH_SD 0x3023
461 #define MASK_SD 0x707f
462 #define CSR_FFLAGS 0x1
465 #define CSR_STATS 0xc0
466 #define CSR_SUP0 0x500
467 #define CSR_SUP1 0x501
468 #define CSR_EPC 0x502
469 #define CSR_BADVADDR 0x503
470 #define CSR_PTBR 0x504
471 #define CSR_ASID 0x505
472 #define CSR_COUNT 0x506
473 #define CSR_COMPARE 0x507
474 #define CSR_EVEC 0x508
475 #define CSR_CAUSE 0x509
476 #define CSR_STATUS 0x50a
477 #define CSR_HARTID 0x50b
478 #define CSR_IMPL 0x50c
479 #define CSR_FATC 0x50d
480 #define CSR_SEND_IPI 0x50e
481 #define CSR_CLEAR_IPI 0x50f
482 #define CSR_RESET 0x51d
483 #define CSR_TOHOST 0x51e
484 #define CSR_FROMHOST 0x51f
485 #define CSR_CYCLE 0xc00
486 #define CSR_TIME 0xc01
487 #define CSR_INSTRET 0xc02
488 #define CSR_UARCH0 0xcc0
489 #define CSR_UARCH1 0xcc1
490 #define CSR_UARCH2 0xcc2
491 #define CSR_UARCH3 0xcc3
492 #define CSR_UARCH4 0xcc4
493 #define CSR_UARCH5 0xcc5
494 #define CSR_UARCH6 0xcc6
495 #define CSR_UARCH7 0xcc7
496 #define CSR_UARCH8 0xcc8
497 #define CSR_UARCH9 0xcc9
498 #define CSR_UARCH10 0xcca
499 #define CSR_UARCH11 0xccb
500 #define CSR_UARCH12 0xccc
501 #define CSR_UARCH13 0xccd
502 #define CSR_UARCH14 0xcce
503 #define CSR_UARCH15 0xccf
504 #define CSR_COUNTH 0x586
505 #define CSR_CYCLEH 0xc80
506 #define CSR_TIMEH 0xc81
507 #define CSR_INSTRETH 0xc82
508 #define CAUSE_MISALIGNED_FETCH 0x0
509 #define CAUSE_FAULT_FETCH 0x1
510 #define CAUSE_ILLEGAL_INSTRUCTION 0x2
511 #define CAUSE_PRIVILEGED_INSTRUCTION 0x3
512 #define CAUSE_FP_DISABLED 0x4
513 #define CAUSE_SYSCALL 0x6
514 #define CAUSE_BREAKPOINT 0x7
515 #define CAUSE_MISALIGNED_LOAD 0x8
516 #define CAUSE_MISALIGNED_STORE 0x9
517 #define CAUSE_FAULT_LOAD 0xa
518 #define CAUSE_FAULT_STORE 0xb
519 #define CAUSE_ACCELERATOR_DISABLED 0xc
522 DECLARE_INSN(fmv_s_x
, MATCH_FMV_S_X
, MASK_FMV_S_X
)
523 DECLARE_INSN(custom1_rs1
, MATCH_CUSTOM1_RS1
, MASK_CUSTOM1_RS1
)
524 DECLARE_INSN(amoxor_w
, MATCH_AMOXOR_W
, MASK_AMOXOR_W
)
525 DECLARE_INSN(remuw
, MATCH_REMUW
, MASK_REMUW
)
526 DECLARE_INSN(fmin_d
, MATCH_FMIN_D
, MASK_FMIN_D
)
527 DECLARE_INSN(amomax_d
, MATCH_AMOMAX_D
, MASK_AMOMAX_D
)
528 DECLARE_INSN(bltu
, MATCH_BLTU
, MASK_BLTU
)
529 DECLARE_INSN(fsgnjn_d
, MATCH_FSGNJN_D
, MASK_FSGNJN_D
)
530 DECLARE_INSN(fmin_s
, MATCH_FMIN_S
, MASK_FMIN_S
)
531 DECLARE_INSN(custom3_rd_rs1_rs2
, MATCH_CUSTOM3_RD_RS1_RS2
, MASK_CUSTOM3_RD_RS1_RS2
)
532 DECLARE_INSN(csrrw
, MATCH_CSRRW
, MASK_CSRRW
)
533 DECLARE_INSN(slliw
, MATCH_SLLIW
, MASK_SLLIW
)
534 DECLARE_INSN(lb
, MATCH_LB
, MASK_LB
)
535 DECLARE_INSN(custom1_rd
, MATCH_CUSTOM1_RD
, MASK_CUSTOM1_RD
)
536 DECLARE_INSN(fmax_s
, MATCH_FMAX_S
, MASK_FMAX_S
)
537 DECLARE_INSN(lh
, MATCH_LH
, MASK_LH
)
538 DECLARE_INSN(fcvt_d_w
, MATCH_FCVT_D_W
, MASK_FCVT_D_W
)
539 DECLARE_INSN(lw
, MATCH_LW
, MASK_LW
)
540 DECLARE_INSN(add
, MATCH_ADD
, MASK_ADD
)
541 DECLARE_INSN(csrrc
, MATCH_CSRRC
, MASK_CSRRC
)
542 DECLARE_INSN(fmax_d
, MATCH_FMAX_D
, MASK_FMAX_D
)
543 DECLARE_INSN(bne
, MATCH_BNE
, MASK_BNE
)
544 DECLARE_INSN(fcvt_s_d
, MATCH_FCVT_S_D
, MASK_FCVT_S_D
)
545 DECLARE_INSN(bgeu
, MATCH_BGEU
, MASK_BGEU
)
546 DECLARE_INSN(fadd_d
, MATCH_FADD_D
, MASK_FADD_D
)
547 DECLARE_INSN(sltiu
, MATCH_SLTIU
, MASK_SLTIU
)
548 DECLARE_INSN(fadd_s
, MATCH_FADD_S
, MASK_FADD_S
)
549 DECLARE_INSN(fclass_d
, MATCH_FCLASS_D
, MASK_FCLASS_D
)
550 DECLARE_INSN(fcvt_s_w
, MATCH_FCVT_S_W
, MASK_FCVT_S_W
)
551 DECLARE_INSN(mul
, MATCH_MUL
, MASK_MUL
)
552 DECLARE_INSN(amominu_d
, MATCH_AMOMINU_D
, MASK_AMOMINU_D
)
553 DECLARE_INSN(fcvt_s_lu
, MATCH_FCVT_S_LU
, MASK_FCVT_S_LU
)
554 DECLARE_INSN(srli
, MATCH_SRLI
, MASK_SRLI
)
555 DECLARE_INSN(amominu_w
, MATCH_AMOMINU_W
, MASK_AMOMINU_W
)
556 DECLARE_INSN(divuw
, MATCH_DIVUW
, MASK_DIVUW
)
557 DECLARE_INSN(mulw
, MATCH_MULW
, MASK_MULW
)
558 DECLARE_INSN(srlw
, MATCH_SRLW
, MASK_SRLW
)
559 DECLARE_INSN(div
, MATCH_DIV
, MASK_DIV
)
560 DECLARE_INSN(fdiv_d
, MATCH_FDIV_D
, MASK_FDIV_D
)
561 DECLARE_INSN(fence
, MATCH_FENCE
, MASK_FENCE
)
562 DECLARE_INSN(custom0_rs1_rs2
, MATCH_CUSTOM0_RS1_RS2
, MASK_CUSTOM0_RS1_RS2
)
563 DECLARE_INSN(fnmsub_s
, MATCH_FNMSUB_S
, MASK_FNMSUB_S
)
564 DECLARE_INSN(fcvt_l_s
, MATCH_FCVT_L_S
, MASK_FCVT_L_S
)
565 DECLARE_INSN(sbreak
, MATCH_SBREAK
, MASK_SBREAK
)
566 DECLARE_INSN(fle_s
, MATCH_FLE_S
, MASK_FLE_S
)
567 DECLARE_INSN(fdiv_s
, MATCH_FDIV_S
, MASK_FDIV_S
)
568 DECLARE_INSN(fle_d
, MATCH_FLE_D
, MASK_FLE_D
)
569 DECLARE_INSN(fence_i
, MATCH_FENCE_I
, MASK_FENCE_I
)
570 DECLARE_INSN(fnmsub_d
, MATCH_FNMSUB_D
, MASK_FNMSUB_D
)
571 DECLARE_INSN(addw
, MATCH_ADDW
, MASK_ADDW
)
572 DECLARE_INSN(sll
, MATCH_SLL
, MASK_SLL
)
573 DECLARE_INSN(xor, MATCH_XOR
, MASK_XOR
)
574 DECLARE_INSN(sub
, MATCH_SUB
, MASK_SUB
)
575 DECLARE_INSN(blt
, MATCH_BLT
, MASK_BLT
)
576 DECLARE_INSN(scall
, MATCH_SCALL
, MASK_SCALL
)
577 DECLARE_INSN(custom2_rd_rs1
, MATCH_CUSTOM2_RD_RS1
, MASK_CUSTOM2_RD_RS1
)
578 DECLARE_INSN(fclass_s
, MATCH_FCLASS_S
, MASK_FCLASS_S
)
579 DECLARE_INSN(sc_w
, MATCH_SC_W
, MASK_SC_W
)
580 DECLARE_INSN(rem
, MATCH_REM
, MASK_REM
)
581 DECLARE_INSN(srliw
, MATCH_SRLIW
, MASK_SRLIW
)
582 DECLARE_INSN(lui
, MATCH_LUI
, MASK_LUI
)
583 DECLARE_INSN(csrrci
, MATCH_CSRRCI
, MASK_CSRRCI
)
584 DECLARE_INSN(addi
, MATCH_ADDI
, MASK_ADDI
)
585 DECLARE_INSN(mulh
, MATCH_MULH
, MASK_MULH
)
586 DECLARE_INSN(fmul_s
, MATCH_FMUL_S
, MASK_FMUL_S
)
587 DECLARE_INSN(csrrsi
, MATCH_CSRRSI
, MASK_CSRRSI
)
588 DECLARE_INSN(srai
, MATCH_SRAI
, MASK_SRAI
)
589 DECLARE_INSN(amoand_d
, MATCH_AMOAND_D
, MASK_AMOAND_D
)
590 DECLARE_INSN(flt_d
, MATCH_FLT_D
, MASK_FLT_D
)
591 DECLARE_INSN(sraw
, MATCH_SRAW
, MASK_SRAW
)
592 DECLARE_INSN(fmul_d
, MATCH_FMUL_D
, MASK_FMUL_D
)
593 DECLARE_INSN(ld
, MATCH_LD
, MASK_LD
)
594 DECLARE_INSN(ori
, MATCH_ORI
, MASK_ORI
)
595 DECLARE_INSN(csrrs
, MATCH_CSRRS
, MASK_CSRRS
)
596 DECLARE_INSN(flt_s
, MATCH_FLT_S
, MASK_FLT_S
)
597 DECLARE_INSN(addiw
, MATCH_ADDIW
, MASK_ADDIW
)
598 DECLARE_INSN(amoand_w
, MATCH_AMOAND_W
, MASK_AMOAND_W
)
599 DECLARE_INSN(feq_s
, MATCH_FEQ_S
, MASK_FEQ_S
)
600 DECLARE_INSN(fsgnjx_d
, MATCH_FSGNJX_D
, MASK_FSGNJX_D
)
601 DECLARE_INSN(sra
, MATCH_SRA
, MASK_SRA
)
602 DECLARE_INSN(bge
, MATCH_BGE
, MASK_BGE
)
603 DECLARE_INSN(sraiw
, MATCH_SRAIW
, MASK_SRAIW
)
604 DECLARE_INSN(srl
, MATCH_SRL
, MASK_SRL
)
605 DECLARE_INSN(custom3_rs1
, MATCH_CUSTOM3_RS1
, MASK_CUSTOM3_RS1
)
606 DECLARE_INSN(fsub_d
, MATCH_FSUB_D
, MASK_FSUB_D
)
607 DECLARE_INSN(custom1_rd_rs1_rs2
, MATCH_CUSTOM1_RD_RS1_RS2
, MASK_CUSTOM1_RD_RS1_RS2
)
608 DECLARE_INSN(fsgnjx_s
, MATCH_FSGNJX_S
, MASK_FSGNJX_S
)
609 DECLARE_INSN(feq_d
, MATCH_FEQ_D
, MASK_FEQ_D
)
610 DECLARE_INSN(custom1_rd_rs1
, MATCH_CUSTOM1_RD_RS1
, MASK_CUSTOM1_RD_RS1
)
611 DECLARE_INSN(fcvt_d_wu
, MATCH_FCVT_D_WU
, MASK_FCVT_D_WU
)
612 DECLARE_INSN(or, MATCH_OR
, MASK_OR
)
613 DECLARE_INSN(fcvt_wu_d
, MATCH_FCVT_WU_D
, MASK_FCVT_WU_D
)
614 DECLARE_INSN(subw
, MATCH_SUBW
, MASK_SUBW
)
615 DECLARE_INSN(fcvt_d_l
, MATCH_FCVT_D_L
, MASK_FCVT_D_L
)
616 DECLARE_INSN(amomaxu_d
, MATCH_AMOMAXU_D
, MASK_AMOMAXU_D
)
617 DECLARE_INSN(xori
, MATCH_XORI
, MASK_XORI
)
618 DECLARE_INSN(amoxor_d
, MATCH_AMOXOR_D
, MASK_AMOXOR_D
)
619 DECLARE_INSN(amomaxu_w
, MATCH_AMOMAXU_W
, MASK_AMOMAXU_W
)
620 DECLARE_INSN(fcvt_wu_s
, MATCH_FCVT_WU_S
, MASK_FCVT_WU_S
)
621 DECLARE_INSN(custom3_rd
, MATCH_CUSTOM3_RD
, MASK_CUSTOM3_RD
)
622 DECLARE_INSN(custom0_rs1
, MATCH_CUSTOM0_RS1
, MASK_CUSTOM0_RS1
)
623 DECLARE_INSN(andi
, MATCH_ANDI
, MASK_ANDI
)
624 DECLARE_INSN(fmv_x_s
, MATCH_FMV_X_S
, MASK_FMV_X_S
)
625 DECLARE_INSN(custom0_rd_rs1_rs2
, MATCH_CUSTOM0_RD_RS1_RS2
, MASK_CUSTOM0_RD_RS1_RS2
)
626 DECLARE_INSN(sret
, MATCH_SRET
, MASK_SRET
)
627 DECLARE_INSN(fnmadd_s
, MATCH_FNMADD_S
, MASK_FNMADD_S
)
628 DECLARE_INSN(jal
, MATCH_JAL
, MASK_JAL
)
629 DECLARE_INSN(lwu
, MATCH_LWU
, MASK_LWU
)
630 DECLARE_INSN(fmv_x_d
, MATCH_FMV_X_D
, MASK_FMV_X_D
)
631 DECLARE_INSN(custom0_rd
, MATCH_CUSTOM0_RD
, MASK_CUSTOM0_RD
)
632 DECLARE_INSN(fcvt_d_s
, MATCH_FCVT_D_S
, MASK_FCVT_D_S
)
633 DECLARE_INSN(fnmadd_d
, MATCH_FNMADD_D
, MASK_FNMADD_D
)
634 DECLARE_INSN(amoadd_d
, MATCH_AMOADD_D
, MASK_AMOADD_D
)
635 DECLARE_INSN(custom3_rd_rs1
, MATCH_CUSTOM3_RD_RS1
, MASK_CUSTOM3_RD_RS1
)
636 DECLARE_INSN(lr_d
, MATCH_LR_D
, MASK_LR_D
)
637 DECLARE_INSN(fcvt_w_s
, MATCH_FCVT_W_S
, MASK_FCVT_W_S
)
638 DECLARE_INSN(mulhsu
, MATCH_MULHSU
, MASK_MULHSU
)
639 DECLARE_INSN(amoadd_w
, MATCH_AMOADD_W
, MASK_AMOADD_W
)
640 DECLARE_INSN(fcvt_d_lu
, MATCH_FCVT_D_LU
, MASK_FCVT_D_LU
)
641 DECLARE_INSN(lr_w
, MATCH_LR_W
, MASK_LR_W
)
642 DECLARE_INSN(custom3_rs1_rs2
, MATCH_CUSTOM3_RS1_RS2
, MASK_CUSTOM3_RS1_RS2
)
643 DECLARE_INSN(fcvt_w_d
, MATCH_FCVT_W_D
, MASK_FCVT_W_D
)
644 DECLARE_INSN(custom1_rs1_rs2
, MATCH_CUSTOM1_RS1_RS2
, MASK_CUSTOM1_RS1_RS2
)
645 DECLARE_INSN(slt
, MATCH_SLT
, MASK_SLT
)
646 DECLARE_INSN(sllw
, MATCH_SLLW
, MASK_SLLW
)
647 DECLARE_INSN(amoor_d
, MATCH_AMOOR_D
, MASK_AMOOR_D
)
648 DECLARE_INSN(slti
, MATCH_SLTI
, MASK_SLTI
)
649 DECLARE_INSN(remu
, MATCH_REMU
, MASK_REMU
)
650 DECLARE_INSN(flw
, MATCH_FLW
, MASK_FLW
)
651 DECLARE_INSN(remw
, MATCH_REMW
, MASK_REMW
)
652 DECLARE_INSN(sltu
, MATCH_SLTU
, MASK_SLTU
)
653 DECLARE_INSN(custom2_rd_rs1_rs2
, MATCH_CUSTOM2_RD_RS1_RS2
, MASK_CUSTOM2_RD_RS1_RS2
)
654 DECLARE_INSN(slli
, MATCH_SLLI
, MASK_SLLI
)
655 DECLARE_INSN(custom2_rd
, MATCH_CUSTOM2_RD
, MASK_CUSTOM2_RD
)
656 DECLARE_INSN(amoor_w
, MATCH_AMOOR_W
, MASK_AMOOR_W
)
657 DECLARE_INSN(beq
, MATCH_BEQ
, MASK_BEQ
)
658 DECLARE_INSN(fld
, MATCH_FLD
, MASK_FLD
)
659 DECLARE_INSN(fsub_s
, MATCH_FSUB_S
, MASK_FSUB_S
)
660 DECLARE_INSN(and, MATCH_AND
, MASK_AND
)
661 DECLARE_INSN(fmv_d_x
, MATCH_FMV_D_X
, MASK_FMV_D_X
)
662 DECLARE_INSN(lbu
, MATCH_LBU
, MASK_LBU
)
663 DECLARE_INSN(custom2_rs1_rs2
, MATCH_CUSTOM2_RS1_RS2
, MASK_CUSTOM2_RS1_RS2
)
664 DECLARE_INSN(fsgnj_s
, MATCH_FSGNJ_S
, MASK_FSGNJ_S
)
665 DECLARE_INSN(custom0
, MATCH_CUSTOM0
, MASK_CUSTOM0
)
666 DECLARE_INSN(custom1
, MATCH_CUSTOM1
, MASK_CUSTOM1
)
667 DECLARE_INSN(custom2
, MATCH_CUSTOM2
, MASK_CUSTOM2
)
668 DECLARE_INSN(custom3
, MATCH_CUSTOM3
, MASK_CUSTOM3
)
669 DECLARE_INSN(amomax_w
, MATCH_AMOMAX_W
, MASK_AMOMAX_W
)
670 DECLARE_INSN(fsgnj_d
, MATCH_FSGNJ_D
, MASK_FSGNJ_D
)
671 DECLARE_INSN(mulhu
, MATCH_MULHU
, MASK_MULHU
)
672 DECLARE_INSN(fcvt_l_d
, MATCH_FCVT_L_D
, MASK_FCVT_L_D
)
673 DECLARE_INSN(fcvt_s_wu
, MATCH_FCVT_S_WU
, MASK_FCVT_S_WU
)
674 DECLARE_INSN(fcvt_lu_s
, MATCH_FCVT_LU_S
, MASK_FCVT_LU_S
)
675 DECLARE_INSN(fcvt_s_l
, MATCH_FCVT_S_L
, MASK_FCVT_S_L
)
676 DECLARE_INSN(custom0_rd_rs1
, MATCH_CUSTOM0_RD_RS1
, MASK_CUSTOM0_RD_RS1
)
677 DECLARE_INSN(auipc
, MATCH_AUIPC
, MASK_AUIPC
)
678 DECLARE_INSN(fcvt_lu_d
, MATCH_FCVT_LU_D
, MASK_FCVT_LU_D
)
679 DECLARE_INSN(csrrwi
, MATCH_CSRRWI
, MASK_CSRRWI
)
680 DECLARE_INSN(sc_d
, MATCH_SC_D
, MASK_SC_D
)
681 DECLARE_INSN(fmadd_s
, MATCH_FMADD_S
, MASK_FMADD_S
)
682 DECLARE_INSN(fsqrt_s
, MATCH_FSQRT_S
, MASK_FSQRT_S
)
683 DECLARE_INSN(amomin_w
, MATCH_AMOMIN_W
, MASK_AMOMIN_W
)
684 DECLARE_INSN(fsgnjn_s
, MATCH_FSGNJN_S
, MASK_FSGNJN_S
)
685 DECLARE_INSN(amoswap_d
, MATCH_AMOSWAP_D
, MASK_AMOSWAP_D
)
686 DECLARE_INSN(fsqrt_d
, MATCH_FSQRT_D
, MASK_FSQRT_D
)
687 DECLARE_INSN(fmadd_d
, MATCH_FMADD_D
, MASK_FMADD_D
)
688 DECLARE_INSN(divw
, MATCH_DIVW
, MASK_DIVW
)
689 DECLARE_INSN(amomin_d
, MATCH_AMOMIN_D
, MASK_AMOMIN_D
)
690 DECLARE_INSN(divu
, MATCH_DIVU
, MASK_DIVU
)
691 DECLARE_INSN(amoswap_w
, MATCH_AMOSWAP_W
, MASK_AMOSWAP_W
)
692 DECLARE_INSN(jalr
, MATCH_JALR
, MASK_JALR
)
693 DECLARE_INSN(fsd
, MATCH_FSD
, MASK_FSD
)
694 DECLARE_INSN(custom2_rs1
, MATCH_CUSTOM2_RS1
, MASK_CUSTOM2_RS1
)
695 DECLARE_INSN(sw
, MATCH_SW
, MASK_SW
)
696 DECLARE_INSN(fmsub_s
, MATCH_FMSUB_S
, MASK_FMSUB_S
)
697 DECLARE_INSN(lhu
, MATCH_LHU
, MASK_LHU
)
698 DECLARE_INSN(sh
, MATCH_SH
, MASK_SH
)
699 DECLARE_INSN(fsw
, MATCH_FSW
, MASK_FSW
)
700 DECLARE_INSN(sb
, MATCH_SB
, MASK_SB
)
701 DECLARE_INSN(fmsub_d
, MATCH_FMSUB_D
, MASK_FMSUB_D
)
702 DECLARE_INSN(sd
, MATCH_SD
, MASK_SD
)
705 DECLARE_CSR(fflags
, CSR_FFLAGS
)
706 DECLARE_CSR(frm
, CSR_FRM
)
707 DECLARE_CSR(fcsr
, CSR_FCSR
)
708 DECLARE_CSR(stats
, CSR_STATS
)
709 DECLARE_CSR(sup0
, CSR_SUP0
)
710 DECLARE_CSR(sup1
, CSR_SUP1
)
711 DECLARE_CSR(epc
, CSR_EPC
)
712 DECLARE_CSR(badvaddr
, CSR_BADVADDR
)
713 DECLARE_CSR(ptbr
, CSR_PTBR
)
714 DECLARE_CSR(asid
, CSR_ASID
)
715 DECLARE_CSR(count
, CSR_COUNT
)
716 DECLARE_CSR(compare
, CSR_COMPARE
)
717 DECLARE_CSR(evec
, CSR_EVEC
)
718 DECLARE_CSR(cause
, CSR_CAUSE
)
719 DECLARE_CSR(status
, CSR_STATUS
)
720 DECLARE_CSR(hartid
, CSR_HARTID
)
721 DECLARE_CSR(impl
, CSR_IMPL
)
722 DECLARE_CSR(fatc
, CSR_FATC
)
723 DECLARE_CSR(send_ipi
, CSR_SEND_IPI
)
724 DECLARE_CSR(clear_ipi
, CSR_CLEAR_IPI
)
725 DECLARE_CSR(reset
, CSR_RESET
)
726 DECLARE_CSR(tohost
, CSR_TOHOST
)
727 DECLARE_CSR(fromhost
, CSR_FROMHOST
)
728 DECLARE_CSR(cycle
, CSR_CYCLE
)
729 DECLARE_CSR(time
, CSR_TIME
)
730 DECLARE_CSR(instret
, CSR_INSTRET
)
731 DECLARE_CSR(uarch0
, CSR_UARCH0
)
732 DECLARE_CSR(uarch1
, CSR_UARCH1
)
733 DECLARE_CSR(uarch2
, CSR_UARCH2
)
734 DECLARE_CSR(uarch3
, CSR_UARCH3
)
735 DECLARE_CSR(uarch4
, CSR_UARCH4
)
736 DECLARE_CSR(uarch5
, CSR_UARCH5
)
737 DECLARE_CSR(uarch6
, CSR_UARCH6
)
738 DECLARE_CSR(uarch7
, CSR_UARCH7
)
739 DECLARE_CSR(uarch8
, CSR_UARCH8
)
740 DECLARE_CSR(uarch9
, CSR_UARCH9
)
741 DECLARE_CSR(uarch10
, CSR_UARCH10
)
742 DECLARE_CSR(uarch11
, CSR_UARCH11
)
743 DECLARE_CSR(uarch12
, CSR_UARCH12
)
744 DECLARE_CSR(uarch13
, CSR_UARCH13
)
745 DECLARE_CSR(uarch14
, CSR_UARCH14
)
746 DECLARE_CSR(uarch15
, CSR_UARCH15
)
747 DECLARE_CSR(counth
, CSR_COUNTH
)
748 DECLARE_CSR(cycleh
, CSR_CYCLEH
)
749 DECLARE_CSR(timeh
, CSR_TIMEH
)
750 DECLARE_CSR(instreth
, CSR_INSTRETH
)
753 DECLARE_CAUSE("fflags", CAUSE_FFLAGS
)
754 DECLARE_CAUSE("frm", CAUSE_FRM
)
755 DECLARE_CAUSE("fcsr", CAUSE_FCSR
)
756 DECLARE_CAUSE("stats", CAUSE_STATS
)
757 DECLARE_CAUSE("sup0", CAUSE_SUP0
)
758 DECLARE_CAUSE("sup1", CAUSE_SUP1
)
759 DECLARE_CAUSE("epc", CAUSE_EPC
)
760 DECLARE_CAUSE("badvaddr", CAUSE_BADVADDR
)
761 DECLARE_CAUSE("ptbr", CAUSE_PTBR
)
762 DECLARE_CAUSE("asid", CAUSE_ASID
)
763 DECLARE_CAUSE("count", CAUSE_COUNT
)
764 DECLARE_CAUSE("compare", CAUSE_COMPARE
)
765 DECLARE_CAUSE("evec", CAUSE_EVEC
)
766 DECLARE_CAUSE("cause", CAUSE_CAUSE
)
767 DECLARE_CAUSE("status", CAUSE_STATUS
)
768 DECLARE_CAUSE("hartid", CAUSE_HARTID
)
769 DECLARE_CAUSE("impl", CAUSE_IMPL
)
770 DECLARE_CAUSE("fatc", CAUSE_FATC
)
771 DECLARE_CAUSE("send_ipi", CAUSE_SEND_IPI
)
772 DECLARE_CAUSE("clear_ipi", CAUSE_CLEAR_IPI
)
773 DECLARE_CAUSE("reset", CAUSE_RESET
)
774 DECLARE_CAUSE("tohost", CAUSE_TOHOST
)
775 DECLARE_CAUSE("fromhost", CAUSE_FROMHOST
)
776 DECLARE_CAUSE("cycle", CAUSE_CYCLE
)
777 DECLARE_CAUSE("time", CAUSE_TIME
)
778 DECLARE_CAUSE("instret", CAUSE_INSTRET
)
779 DECLARE_CAUSE("uarch0", CAUSE_UARCH0
)
780 DECLARE_CAUSE("uarch1", CAUSE_UARCH1
)
781 DECLARE_CAUSE("uarch2", CAUSE_UARCH2
)
782 DECLARE_CAUSE("uarch3", CAUSE_UARCH3
)
783 DECLARE_CAUSE("uarch4", CAUSE_UARCH4
)
784 DECLARE_CAUSE("uarch5", CAUSE_UARCH5
)
785 DECLARE_CAUSE("uarch6", CAUSE_UARCH6
)
786 DECLARE_CAUSE("uarch7", CAUSE_UARCH7
)
787 DECLARE_CAUSE("uarch8", CAUSE_UARCH8
)
788 DECLARE_CAUSE("uarch9", CAUSE_UARCH9
)
789 DECLARE_CAUSE("uarch10", CAUSE_UARCH10
)
790 DECLARE_CAUSE("uarch11", CAUSE_UARCH11
)
791 DECLARE_CAUSE("uarch12", CAUSE_UARCH12
)
792 DECLARE_CAUSE("uarch13", CAUSE_UARCH13
)
793 DECLARE_CAUSE("uarch14", CAUSE_UARCH14
)
794 DECLARE_CAUSE("uarch15", CAUSE_UARCH15
)
795 DECLARE_CAUSE("counth", CAUSE_COUNTH
)
796 DECLARE_CAUSE("cycleh", CAUSE_CYCLEH
)
797 DECLARE_CAUSE("timeh", CAUSE_TIMEH
)
798 DECLARE_CAUSE("instreth", CAUSE_INSTRETH
)