riscv/execute.h

   1 /* Automatically generated by parse-opcodes */
   2 switch((insn.bits >> 0x0) & 0x7f)
   3 {
   4   case 0x0:
   5   {
   6     #include "insns/c_addi.h"
   7     break;
   8   }
   9   case 0x3:
  10   {
  11     switch((insn.bits >> 0x7) & 0x7)
  12     {
  13       case 0x0:
  14       {
  15         #include "insns/lb.h"
  16         break;
  17       }
  18       case 0x1:
  19       {
  20         #include "insns/lh.h"
  21         break;
  22       }
  23       case 0x2:
  24       {
  25         #include "insns/lw.h"
  26         break;
  27       }
  28       case 0x3:
  29       {
  30         #include "insns/ld.h"
  31         break;
  32       }
  33       case 0x4:
  34       {
  35         #include "insns/lbu.h"
  36         break;
  37       }
  38       case 0x5:
  39       {
  40         #include "insns/lhu.h"
  41         break;
  42       }
  43       case 0x6:
  44       {
  45         #include "insns/lwu.h"
  46         break;
  47       }
  48       default:
  49       {
  50         throw trap_illegal_instruction;
  51       }
  52     }
  53     break;
  54   }
  55   case 0x7:
  56   {
  57     switch((insn.bits >> 0x7) & 0x7)
  58     {
  59       case 0x2:
  60       {
  61         #include "insns/flw.h"
  62         break;
  63       }
  64       case 0x3:
  65       {
  66         #include "insns/fld.h"
  67         break;
  68       }
  69       default:
  70       {
  71         throw trap_illegal_instruction;
  72       }
  73     }
  74     break;
  75   }
  76   case 0xb:
  77   {
  78     switch((insn.bits >> 0x7) & 0x7)
  79     {
  80       case 0x0:
  81       {
  82         if((insn.bits & 0x1ffff) == 0x280b)
  83         {
  84           #include "insns/sbseg_v.h"
  85           break;
  86         }
  87         if((insn.bits & 0x1ffff) == 0x100b)
  88         {
  89           #include "insns/lbst_v.h"
  90           break;
  91         }
  92         if((insn.bits & 0x1ffff) == 0x180b)
  93         {
  94           #include "insns/sbst_v.h"
  95           break;
  96         }
  97         if((insn.bits & 0x3fffff) == 0xb)
  98         {
  99           #include "insns/lb_v.h"
 100           break;
 101         }
 102         if((insn.bits & 0x1ffff) == 0x200b)
 103         {
 104           #include "insns/lbseg_v.h"
 105           break;
 106         }
 107         if((insn.bits & 0x3fffff) == 0x1000b)
 108         {
 109           #include "insns/mov_vv.h"
 110           break;
 111         }
 112         if((insn.bits & 0x3fffff) == 0x1800b)
 113         {
 114           #include "insns/fmov_vv.h"
 115           break;
 116         }
 117         if((insn.bits & 0x3fffff) == 0x80b)
 118         {
 119           #include "insns/sb_v.h"
 120           break;
 121         }
 122         throw trap_illegal_instruction;
 123       }
 124       case 0x1:
 125       {
 126         if((insn.bits & 0x1ffff) == 0x208b)
 127         {
 128           #include "insns/lhseg_v.h"
 129           break;
 130         }
 131         if((insn.bits & 0x1ffff) == 0x108b)
 132         {
 133           #include "insns/lhst_v.h"
 134           break;
 135         }
 136         if((insn.bits & 0x3fffff) == 0x1008b)
 137         {
 138           #include "insns/mov_sv.h"
 139           break;
 140         }
 141         if((insn.bits & 0x3fffff) == 0x1808b)
 142         {
 143           #include "insns/fmov_sv.h"
 144           break;
 145         }
 146         if((insn.bits & 0x3fffff) == 0x8b)
 147         {
 148           #include "insns/lh_v.h"
 149           break;
 150         }
 151         if((insn.bits & 0x3fffff) == 0x88b)
 152         {
 153           #include "insns/sh_v.h"
 154           break;
 155         }
 156         if((insn.bits & 0x1ffff) == 0x288b)
 157         {
 158           #include "insns/shseg_v.h"
 159           break;
 160         }
 161         if((insn.bits & 0x1ffff) == 0x188b)
 162         {
 163           #include "insns/shst_v.h"
 164           break;
 165         }
 166         throw trap_illegal_instruction;
 167       }
 168       case 0x2:
 169       {
 170         if((insn.bits & 0x3fffff) == 0x10b)
 171         {
 172           #include "insns/lw_v.h"
 173           break;
 174         }
 175         if((insn.bits & 0x1ffff) == 0x1810b)
 176         {
 177           #include "insns/fmov_su.h"
 178           break;
 179         }
 180         if((insn.bits & 0x1ffff) == 0x290b)
 181         {
 182           #include "insns/swseg_v.h"
 183           break;
 184         }
 185         if((insn.bits & 0x1ffff) == 0x1010b)
 186         {
 187           #include "insns/mov_su.h"
 188           break;
 189         }
 190         if((insn.bits & 0x1ffff) == 0x1d0b)
 191         {
 192           #include "insns/fswst_v.h"
 193           break;
 194         }
 195         if((insn.bits & 0x1ffff) == 0x190b)
 196         {
 197           #include "insns/swst_v.h"
 198           break;
 199         }
 200         if((insn.bits & 0x3fffff) == 0xd0b)
 201         {
 202           #include "insns/fsw_v.h"
 203           break;
 204         }
 205         if((insn.bits & 0x1ffff) == 0x250b)
 206         {
 207           #include "insns/flwseg_v.h"
 208           break;
 209         }
 210         if((insn.bits & 0x3fffff) == 0x50b)
 211         {
 212           #include "insns/flw_v.h"
 213           break;
 214         }
 215         if((insn.bits & 0x3fffff) == 0x90b)
 216         {
 217           #include "insns/sw_v.h"
 218           break;
 219         }
 220         if((insn.bits & 0x1ffff) == 0x150b)
 221         {
 222           #include "insns/flwst_v.h"
 223           break;
 224         }
 225         if((insn.bits & 0x1ffff) == 0x210b)
 226         {
 227           #include "insns/lwseg_v.h"
 228           break;
 229         }
 230         if((insn.bits & 0x1ffff) == 0x2d0b)
 231         {
 232           #include "insns/fswseg_v.h"
 233           break;
 234         }
 235         if((insn.bits & 0x1ffff) == 0x110b)
 236         {
 237           #include "insns/lwst_v.h"
 238           break;
 239         }
 240         throw trap_illegal_instruction;
 241       }
 242       case 0x3:
 243       {
 244         if((insn.bits & 0x1ffff) == 0x218b)
 245         {
 246           #include "insns/ldseg_v.h"
 247           break;
 248         }
 249         if((insn.bits & 0x3fffff) == 0x58b)
 250         {
 251           #include "insns/fld_v.h"
 252           break;
 253         }
 254         if((insn.bits & 0x3fffff) == 0x18b)
 255         {
 256           #include "insns/ld_v.h"
 257           break;
 258         }
 259         if((insn.bits & 0x3fffff) == 0xd8b)
 260         {
 261           #include "insns/fsd_v.h"
 262           break;
 263         }
 264         if((insn.bits & 0x1ffff) == 0x2d8b)
 265         {
 266           #include "insns/fsdseg_v.h"
 267           break;
 268         }
 269         if((insn.bits & 0x1ffff) == 0x1d8b)
 270         {
 271           #include "insns/fsdst_v.h"
 272           break;
 273         }
 274         if((insn.bits & 0x1ffff) == 0x118b)
 275         {
 276           #include "insns/ldst_v.h"
 277           break;
 278         }
 279         if((insn.bits & 0x1ffff) == 0x258b)
 280         {
 281           #include "insns/fldseg_v.h"
 282           break;
 283         }
 284         if((insn.bits & 0x1ffff) == 0x1018b)
 285         {
 286           #include "insns/mov_us.h"
 287           break;
 288         }
 289         if((insn.bits & 0x1ffff) == 0x158b)
 290         {
 291           #include "insns/fldst_v.h"
 292           break;
 293         }
 294         if((insn.bits & 0x1ffff) == 0x298b)
 295         {
 296           #include "insns/sdseg_v.h"
 297           break;
 298         }
 299         if((insn.bits & 0x1ffff) == 0x1818b)
 300         {
 301           #include "insns/fmov_us.h"
 302           break;
 303         }
 304         if((insn.bits & 0x3fffff) == 0x98b)
 305         {
 306           #include "insns/sd_v.h"
 307           break;
 308         }
 309         if((insn.bits & 0x1ffff) == 0x198b)
 310         {
 311           #include "insns/sdst_v.h"
 312           break;
 313         }
 314         throw trap_illegal_instruction;
 315       }
 316       case 0x4:
 317       {
 318         if((insn.bits & 0x3fffff) == 0x20b)
 319         {
 320           #include "insns/lbu_v.h"
 321           break;
 322         }
 323         if((insn.bits & 0x1ffff) == 0x220b)
 324         {
 325           #include "insns/lbuseg_v.h"
 326           break;
 327         }
 328         if((insn.bits & 0x1ffff) == 0x120b)
 329         {
 330           #include "insns/lbust_v.h"
 331           break;
 332         }
 333         throw trap_illegal_instruction;
 334       }
 335       case 0x5:
 336       {
 337         if((insn.bits & 0x1ffff) == 0x128b)
 338         {
 339           #include "insns/lhust_v.h"
 340           break;
 341         }
 342         if((insn.bits & 0x3fffff) == 0x28b)
 343         {
 344           #include "insns/lhu_v.h"
 345           break;
 346         }
 347         if((insn.bits & 0x1ffff) == 0x228b)
 348         {
 349           #include "insns/lhuseg_v.h"
 350           break;
 351         }
 352         throw trap_illegal_instruction;
 353       }
 354       case 0x6:
 355       {
 356         if((insn.bits & 0x1ffff) == 0x230b)
 357         {
 358           #include "insns/lwuseg_v.h"
 359           break;
 360         }
 361         if((insn.bits & 0x3fffff) == 0x30b)
 362         {
 363           #include "insns/lwu_v.h"
 364           break;
 365         }
 366         if((insn.bits & 0x1ffff) == 0x130b)
 367         {
 368           #include "insns/lwust_v.h"
 369           break;
 370         }
 371         throw trap_illegal_instruction;
 372       }
 373       default:
 374       {
 375         throw trap_illegal_instruction;
 376       }
 377     }
 378     break;
 379   }
 380   case 0xf:
 381   {
 382     switch((insn.bits >> 0x7) & 0x7)
 383     {
 384       case 0x0:
 385       {
 386         if((insn.bits & 0xfff) == 0x80f)
 387         {
 388           #include "insns/sbsegst_v.h"
 389           break;
 390         }
 391         if((insn.bits & 0xfff) == 0xf)
 392         {
 393           #include "insns/lbsegst_v.h"
 394           break;
 395         }
 396         throw trap_illegal_instruction;
 397       }
 398       case 0x1:
 399       {
 400         if((insn.bits & 0xfff) == 0x88f)
 401         {
 402           #include "insns/shsegst_v.h"
 403           break;
 404         }
 405         if((insn.bits & 0xfff) == 0x8f)
 406         {
 407           #include "insns/lhsegst_v.h"
 408           break;
 409         }
 410         throw trap_illegal_instruction;
 411       }
 412       case 0x2:
 413       {
 414         if((insn.bits & 0xfff) == 0xd0f)
 415         {
 416           #include "insns/fswsegst_v.h"
 417           break;
 418         }
 419         if((insn.bits & 0xfff) == 0x50f)
 420         {
 421           #include "insns/flwsegst_v.h"
 422           break;
 423         }
 424         if((insn.bits & 0xfff) == 0x10f)
 425         {
 426           #include "insns/lwsegst_v.h"
 427           break;
 428         }
 429         if((insn.bits & 0xfff) == 0x90f)
 430         {
 431           #include "insns/swsegst_v.h"
 432           break;
 433         }
 434         throw trap_illegal_instruction;
 435       }
 436       case 0x3:
 437       {
 438         if((insn.bits & 0xfff) == 0x18f)
 439         {
 440           #include "insns/ldsegst_v.h"
 441           break;
 442         }
 443         if((insn.bits & 0xfff) == 0x98f)
 444         {
 445           #include "insns/sdsegst_v.h"
 446           break;
 447         }
 448         if((insn.bits & 0xfff) == 0x58f)
 449         {
 450           #include "insns/fldsegst_v.h"
 451           break;
 452         }
 453         if((insn.bits & 0xfff) == 0xd8f)
 454         {
 455           #include "insns/fsdsegst_v.h"
 456           break;
 457         }
 458         throw trap_illegal_instruction;
 459       }
 460       case 0x4:
 461       {
 462         if((insn.bits & 0xfff) == 0x20f)
 463         {
 464           #include "insns/lbusegst_v.h"
 465           break;
 466         }
 467         throw trap_illegal_instruction;
 468       }
 469       case 0x5:
 470       {
 471         if((insn.bits & 0xfff) == 0x28f)
 472         {
 473           #include "insns/lhusegst_v.h"
 474           break;
 475         }
 476         throw trap_illegal_instruction;
 477       }
 478       case 0x6:
 479       {
 480         if((insn.bits & 0xfff) == 0x30f)
 481         {
 482           #include "insns/lwusegst_v.h"
 483           break;
 484         }
 485         throw trap_illegal_instruction;
 486       }
 487       default:
 488       {
 489         throw trap_illegal_instruction;
 490       }
 491     }
 492     break;
 493   }
 494   case 0x13:
 495   {
 496     switch((insn.bits >> 0x7) & 0x7)
 497     {
 498       case 0x0:
 499       {
 500         #include "insns/addi.h"
 501         break;
 502       }
 503       case 0x1:
 504       {
 505         if((insn.bits & 0x3f03ff) == 0x93)
 506         {
 507           #include "insns/slli.h"
 508           break;
 509         }
 510         throw trap_illegal_instruction;
 511       }
 512       case 0x2:
 513       {
 514         #include "insns/slti.h"
 515         break;
 516       }
 517       case 0x3:
 518       {
 519         #include "insns/sltiu.h"
 520         break;
 521       }
 522       case 0x4:
 523       {
 524         #include "insns/xori.h"
 525         break;
 526       }
 527       case 0x5:
 528       {
 529         if((insn.bits & 0x3f03ff) == 0x293)
 530         {
 531           #include "insns/srli.h"
 532           break;
 533         }
 534         if((insn.bits & 0x3f03ff) == 0x10293)
 535         {
 536           #include "insns/srai.h"
 537           break;
 538         }
 539         throw trap_illegal_instruction;
 540       }
 541       case 0x6:
 542       {
 543         #include "insns/ori.h"
 544         break;
 545       }
 546       case 0x7:
 547       {
 548         #include "insns/andi.h"
 549         break;
 550       }
 551       default:
 552       {
 553         throw trap_illegal_instruction;
 554       }
 555     }
 556     break;
 557   }
 558   case 0x1b:
 559   {
 560     switch((insn.bits >> 0x7) & 0x7)
 561     {
 562       case 0x0:
 563       {
 564         #include "insns/addiw.h"
 565         break;
 566       }
 567       case 0x1:
 568       {
 569         if((insn.bits & 0x3f83ff) == 0x9b)
 570         {
 571           #include "insns/slliw.h"
 572           break;
 573         }
 574         throw trap_illegal_instruction;
 575       }
 576       case 0x5:
 577       {
 578         if((insn.bits & 0x3f83ff) == 0x29b)
 579         {
 580           #include "insns/srliw.h"
 581           break;
 582         }
 583         if((insn.bits & 0x3f83ff) == 0x1029b)
 584         {
 585           #include "insns/sraiw.h"
 586           break;
 587         }
 588         throw trap_illegal_instruction;
 589       }
 590       default:
 591       {
 592         throw trap_illegal_instruction;
 593       }
 594     }
 595     break;
 596   }
 597   case 0x20:
 598   {
 599     #include "insns/c_addi.h"
 600     break;
 601   }
 602   case 0x23:
 603   {
 604     switch((insn.bits >> 0x7) & 0x7)
 605     {
 606       case 0x0:
 607       {
 608         #include "insns/sb.h"
 609         break;
 610       }
 611       case 0x1:
 612       {
 613         #include "insns/sh.h"
 614         break;
 615       }
 616       case 0x2:
 617       {
 618         #include "insns/sw.h"
 619         break;
 620       }
 621       case 0x3:
 622       {
 623         #include "insns/sd.h"
 624         break;
 625       }
 626       default:
 627       {
 628         throw trap_illegal_instruction;
 629       }
 630     }
 631     break;
 632   }
 633   case 0x27:
 634   {
 635     switch((insn.bits >> 0x7) & 0x7)
 636     {
 637       case 0x2:
 638       {
 639         #include "insns/fsw.h"
 640         break;
 641       }
 642       case 0x3:
 643       {
 644         #include "insns/fsd.h"
 645         break;
 646       }
 647       default:
 648       {
 649         throw trap_illegal_instruction;
 650       }
 651     }
 652     break;
 653   }
 654   case 0x2b:
 655   {
 656     switch((insn.bits >> 0x7) & 0x7)
 657     {
 658       case 0x2:
 659       {
 660         if((insn.bits & 0x1ffff) == 0x192b)
 661         {
 662           #include "insns/amominu_w.h"
 663           break;
 664         }
 665         if((insn.bits & 0x1ffff) == 0x92b)
 666         {
 667           #include "insns/amoand_w.h"
 668           break;
 669         }
 670         if((insn.bits & 0x1ffff) == 0x1d2b)
 671         {
 672           #include "insns/amomaxu_w.h"
 673           break;
 674         }
 675         if((insn.bits & 0x1ffff) == 0x152b)
 676         {
 677           #include "insns/amomax_w.h"
 678           break;
 679         }
 680         if((insn.bits & 0x1ffff) == 0x12b)
 681         {
 682           #include "insns/amoadd_w.h"
 683           break;
 684         }
 685         if((insn.bits & 0x1ffff) == 0xd2b)
 686         {
 687           #include "insns/amoor_w.h"
 688           break;
 689         }
 690         if((insn.bits & 0x1ffff) == 0x112b)
 691         {
 692           #include "insns/amomin_w.h"
 693           break;
 694         }
 695         if((insn.bits & 0x1ffff) == 0x52b)
 696         {
 697           #include "insns/amoswap_w.h"
 698           break;
 699         }
 700         throw trap_illegal_instruction;
 701       }
 702       case 0x3:
 703       {
 704         if((insn.bits & 0x1ffff) == 0x19ab)
 705         {
 706           #include "insns/amominu_d.h"
 707           break;
 708         }
 709         if((insn.bits & 0x1ffff) == 0x9ab)
 710         {
 711           #include "insns/amoand_d.h"
 712           break;
 713         }
 714         if((insn.bits & 0x1ffff) == 0x1dab)
 715         {
 716           #include "insns/amomaxu_d.h"
 717           break;
 718         }
 719         if((insn.bits & 0x1ffff) == 0x1ab)
 720         {
 721           #include "insns/amoadd_d.h"
 722           break;
 723         }
 724         if((insn.bits & 0x1ffff) == 0x15ab)
 725         {
 726           #include "insns/amomax_d.h"
 727           break;
 728         }
 729         if((insn.bits & 0x1ffff) == 0xdab)
 730         {
 731           #include "insns/amoor_d.h"
 732           break;
 733         }
 734         if((insn.bits & 0x1ffff) == 0x5ab)
 735         {
 736           #include "insns/amoswap_d.h"
 737           break;
 738         }
 739         if((insn.bits & 0x1ffff) == 0x11ab)
 740         {
 741           #include "insns/amomin_d.h"
 742           break;
 743         }
 744         throw trap_illegal_instruction;
 745       }
 746       default:
 747       {
 748         throw trap_illegal_instruction;
 749       }
 750     }
 751     break;
 752   }
 753   case 0x2f:
 754   {
 755     switch((insn.bits >> 0x7) & 0x7)
 756     {
 757       case 0x1:
 758       {
 759         #include "insns/fence_i.h"
 760         break;
 761       }
 762       case 0x2:
 763       {
 764         #include "insns/fence.h"
 765         break;
 766       }
 767       case 0x4:
 768       {
 769         #include "insns/fence_l_v.h"
 770         break;
 771       }
 772       case 0x5:
 773       {
 774         #include "insns/fence_g_v.h"
 775         break;
 776       }
 777       case 0x6:
 778       {
 779         #include "insns/fence_l_cv.h"
 780         break;
 781       }
 782       case 0x7:
 783       {
 784         #include "insns/fence_g_cv.h"
 785         break;
 786       }
 787       default:
 788       {
 789         throw trap_illegal_instruction;
 790       }
 791     }
 792     break;
 793   }
 794   case 0x33:
 795   {
 796     switch((insn.bits >> 0x7) & 0x7)
 797     {
 798       case 0x0:
 799       {
 800         if((insn.bits & 0x1ffff) == 0x33)
 801         {
 802           #include "insns/add.h"
 803           break;
 804         }
 805         if((insn.bits & 0x1ffff) == 0x433)
 806         {
 807           #include "insns/mul.h"
 808           break;
 809         }
 810         if((insn.bits & 0x1ffff) == 0x10033)
 811         {
 812           #include "insns/sub.h"
 813           break;
 814         }
 815         throw trap_illegal_instruction;
 816       }
 817       case 0x1:
 818       {
 819         if((insn.bits & 0x1ffff) == 0xb3)
 820         {
 821           #include "insns/sll.h"
 822           break;
 823         }
 824         if((insn.bits & 0x1ffff) == 0x4b3)
 825         {
 826           #include "insns/mulh.h"
 827           break;
 828         }
 829         throw trap_illegal_instruction;
 830       }
 831       case 0x2:
 832       {
 833         if((insn.bits & 0x1ffff) == 0x533)
 834         {
 835           #include "insns/mulhsu.h"
 836           break;
 837         }
 838         if((insn.bits & 0x1ffff) == 0x133)
 839         {
 840           #include "insns/slt.h"
 841           break;
 842         }
 843         throw trap_illegal_instruction;
 844       }
 845       case 0x3:
 846       {
 847         if((insn.bits & 0x1ffff) == 0x1b3)
 848         {
 849           #include "insns/sltu.h"
 850           break;
 851         }
 852         if((insn.bits & 0x1ffff) == 0x5b3)
 853         {
 854           #include "insns/mulhu.h"
 855           break;
 856         }
 857         throw trap_illegal_instruction;
 858       }
 859       case 0x4:
 860       {
 861         if((insn.bits & 0x1ffff) == 0x633)
 862         {
 863           #include "insns/div.h"
 864           break;
 865         }
 866         if((insn.bits & 0x1ffff) == 0x233)
 867         {
 868           #include "insns/xor.h"
 869           break;
 870         }
 871         throw trap_illegal_instruction;
 872       }
 873       case 0x5:
 874       {
 875         if((insn.bits & 0x1ffff) == 0x102b3)
 876         {
 877           #include "insns/sra.h"
 878           break;
 879         }
 880         if((insn.bits & 0x1ffff) == 0x2b3)
 881         {
 882           #include "insns/srl.h"
 883           break;
 884         }
 885         if((insn.bits & 0x1ffff) == 0x6b3)
 886         {
 887           #include "insns/divu.h"
 888           break;
 889         }
 890         throw trap_illegal_instruction;
 891       }
 892       case 0x6:
 893       {
 894         if((insn.bits & 0x1ffff) == 0x733)
 895         {
 896           #include "insns/rem.h"
 897           break;
 898         }
 899         if((insn.bits & 0x1ffff) == 0x333)
 900         {
 901           #include "insns/or.h"
 902           break;
 903         }
 904         throw trap_illegal_instruction;
 905       }
 906       case 0x7:
 907       {
 908         if((insn.bits & 0x1ffff) == 0x7b3)
 909         {
 910           #include "insns/remu.h"
 911           break;
 912         }
 913         if((insn.bits & 0x1ffff) == 0x3b3)
 914         {
 915           #include "insns/and.h"
 916           break;
 917         }
 918         throw trap_illegal_instruction;
 919       }
 920       default:
 921       {
 922         throw trap_illegal_instruction;
 923       }
 924     }
 925     break;
 926   }
 927   case 0x37:
 928   {
 929     #include "insns/lui.h"
 930     break;
 931   }
 932   case 0x3b:
 933   {
 934     switch((insn.bits >> 0x7) & 0x7)
 935     {
 936       case 0x0:
 937       {
 938         if((insn.bits & 0x1ffff) == 0x43b)
 939         {
 940           #include "insns/mulw.h"
 941           break;
 942         }
 943         if((insn.bits & 0x1ffff) == 0x3b)
 944         {
 945           #include "insns/addw.h"
 946           break;
 947         }
 948         if((insn.bits & 0x1ffff) == 0x1003b)
 949         {
 950           #include "insns/subw.h"
 951           break;
 952         }
 953         throw trap_illegal_instruction;
 954       }
 955       case 0x1:
 956       {
 957         if((insn.bits & 0x1ffff) == 0xbb)
 958         {
 959           #include "insns/sllw.h"
 960           break;
 961         }
 962         throw trap_illegal_instruction;
 963       }
 964       case 0x4:
 965       {
 966         if((insn.bits & 0x1ffff) == 0x63b)
 967         {
 968           #include "insns/divw.h"
 969           break;
 970         }
 971         throw trap_illegal_instruction;
 972       }
 973       case 0x5:
 974       {
 975         if((insn.bits & 0x1ffff) == 0x6bb)
 976         {
 977           #include "insns/divuw.h"
 978           break;
 979         }
 980         if((insn.bits & 0x1ffff) == 0x2bb)
 981         {
 982           #include "insns/srlw.h"
 983           break;
 984         }
 985         if((insn.bits & 0x1ffff) == 0x102bb)
 986         {
 987           #include "insns/sraw.h"
 988           break;
 989         }
 990         throw trap_illegal_instruction;
 991       }
 992       case 0x6:
 993       {
 994         if((insn.bits & 0x1ffff) == 0x73b)
 995         {
 996           #include "insns/remw.h"
 997           break;
 998         }
 999         throw trap_illegal_instruction;
1000       }
1001       case 0x7:
1002       {
1003         if((insn.bits & 0x1ffff) == 0x7bb)
1004         {
1005           #include "insns/remuw.h"
1006           break;
1007         }
1008         throw trap_illegal_instruction;
1009       }
1010       default:
1011       {
1012         throw trap_illegal_instruction;
1013       }
1014     }
1015     break;
1016   }
1017   case 0x40:
1018   {
1019     #include "insns/c_addi.h"
1020     break;
1021   }
1022   case 0x43:
1023   {
1024     switch((insn.bits >> 0x7) & 0x7)
1025     {
1026       case 0x0:
1027       {
1028         #include "insns/fmadd_s.h"
1029         break;
1030       }
1031       case 0x1:
1032       {
1033         #include "insns/fmadd_d.h"
1034         break;
1035       }
1036       case 0x4:
1037       {
1038         #include "insns/fmadd_s.h"
1039         break;
1040       }
1041       case 0x5:
1042       {
1043         #include "insns/fmadd_d.h"
1044         break;
1045       }
1046       default:
1047       {
1048         throw trap_illegal_instruction;
1049       }
1050     }
1051     break;
1052   }
1053   case 0x47:
1054   {
1055     switch((insn.bits >> 0x7) & 0x7)
1056     {
1057       case 0x0:
1058       {
1059         #include "insns/fmsub_s.h"
1060         break;
1061       }
1062       case 0x1:
1063       {
1064         #include "insns/fmsub_d.h"
1065         break;
1066       }
1067       case 0x4:
1068       {
1069         #include "insns/fmsub_s.h"
1070         break;
1071       }
1072       case 0x5:
1073       {
1074         #include "insns/fmsub_d.h"
1075         break;
1076       }
1077       default:
1078       {
1079         throw trap_illegal_instruction;
1080       }
1081     }
1082     break;
1083   }
1084   case 0x4b:
1085   {
1086     switch((insn.bits >> 0x7) & 0x7)
1087     {
1088       case 0x0:
1089       {
1090         #include "insns/fnmsub_s.h"
1091         break;
1092       }
1093       case 0x1:
1094       {
1095         #include "insns/fnmsub_d.h"
1096         break;
1097       }
1098       case 0x4:
1099       {
1100         #include "insns/fnmsub_s.h"
1101         break;
1102       }
1103       case 0x5:
1104       {
1105         #include "insns/fnmsub_d.h"
1106         break;
1107       }
1108       default:
1109       {
1110         throw trap_illegal_instruction;
1111       }
1112     }
1113     break;
1114   }
1115   case 0x4f:
1116   {
1117     switch((insn.bits >> 0x7) & 0x7)
1118     {
1119       case 0x0:
1120       {
1121         #include "insns/fnmadd_s.h"
1122         break;
1123       }
1124       case 0x1:
1125       {
1126         #include "insns/fnmadd_d.h"
1127         break;
1128       }
1129       case 0x4:
1130       {
1131         #include "insns/fnmadd_s.h"
1132         break;
1133       }
1134       case 0x5:
1135       {
1136         #include "insns/fnmadd_d.h"
1137         break;
1138       }
1139       default:
1140       {
1141         throw trap_illegal_instruction;
1142       }
1143     }
1144     break;
1145   }
1146   case 0x53:
1147   {
1148     switch((insn.bits >> 0x7) & 0x7)
1149     {
1150       case 0x0:
1151       {
1152         if((insn.bits & 0x3ff1ff) == 0x9053)
1153         {
1154           #include "insns/fcvt_lu_s.h"
1155           break;
1156         }
1157         if((insn.bits & 0x1ffff) == 0x18053)
1158         {
1159           #include "insns/fmin_s.h"
1160           break;
1161         }
1162         if((insn.bits & 0x3ff1ff) == 0x11053)
1163         {
1164           #include "insns/fcvt_s_d.h"
1165           break;
1166         }
1167         if((insn.bits & 0x3ff1ff) == 0xe053)
1168         {
1169           #include "insns/fcvt_s_w.h"
1170           break;
1171         }
1172         if((insn.bits & 0x7c1ffff) == 0x1c053)
1173         {
1174           #include "insns/mftx_s.h"
1175           break;
1176         }
1177         if((insn.bits & 0x3ff1ff) == 0x8053)
1178         {
1179           #include "insns/fcvt_l_s.h"
1180           break;
1181         }
1182         if((insn.bits & 0x1ffff) == 0x17053)
1183         {
1184           #include "insns/fle_s.h"
1185           break;
1186         }
1187         if((insn.bits & 0x7ffffff) == 0x1d053)
1188         {
1189           #include "insns/mffsr.h"
1190           break;
1191         }
1192         if((insn.bits & 0x1f1ff) == 0x3053)
1193         {
1194           #include "insns/fdiv_s.h"
1195           break;
1196         }
1197         if((insn.bits & 0x3fffff) == 0x1f053)
1198         {
1199           #include "insns/mtfsr.h"
1200           break;
1201         }
1202         if((insn.bits & 0x3ff1ff) == 0xd053)
1203         {
1204           #include "insns/fcvt_s_lu.h"
1205           break;
1206         }
1207         if((insn.bits & 0x1f1ff) == 0x2053)
1208         {
1209           #include "insns/fmul_s.h"
1210           break;
1211         }
1212         if((insn.bits & 0x1ffff) == 0x16053)
1213         {
1214           #include "insns/flt_s.h"
1215           break;
1216         }
1217         if((insn.bits & 0x1ffff) == 0x15053)
1218         {
1219           #include "insns/feq_s.h"
1220           break;
1221         }
1222         if((insn.bits & 0x1ffff) == 0x7053)
1223         {
1224           #include "insns/fsgnjx_s.h"
1225           break;
1226         }
1227         if((insn.bits & 0x1ffff) == 0x19053)
1228         {
1229           #include "insns/fmax_s.h"
1230           break;
1231         }
1232         if((insn.bits & 0x3ff1ff) == 0xb053)
1233         {
1234           #include "insns/fcvt_wu_s.h"
1235           break;
1236         }
1237         if((insn.bits & 0x3ff1ff) == 0xa053)
1238         {
1239           #include "insns/fcvt_w_s.h"
1240           break;
1241         }
1242         if((insn.bits & 0x3fffff) == 0x1e053)
1243         {
1244           #include "insns/mxtf_s.h"
1245           break;
1246         }
1247         if((insn.bits & 0x1f1ff) == 0x1053)
1248         {
1249           #include "insns/fsub_s.h"
1250           break;
1251         }
1252         if((insn.bits & 0x1ffff) == 0x5053)
1253         {
1254           #include "insns/fsgnj_s.h"
1255           break;
1256         }
1257         if((insn.bits & 0x3ff1ff) == 0xf053)
1258         {
1259           #include "insns/fcvt_s_wu.h"
1260           break;
1261         }
1262         if((insn.bits & 0x3ff1ff) == 0xc053)
1263         {
1264           #include "insns/fcvt_s_l.h"
1265           break;
1266         }
1267         if((insn.bits & 0x3ff1ff) == 0x4053)
1268         {
1269           #include "insns/fsqrt_s.h"
1270           break;
1271         }
1272         if((insn.bits & 0x1ffff) == 0x6053)
1273         {
1274           #include "insns/fsgnjn_s.h"
1275           break;
1276         }
1277         if((insn.bits & 0x1f1ff) == 0x53)
1278         {
1279           #include "insns/fadd_s.h"
1280           break;
1281         }
1282         throw trap_illegal_instruction;
1283       }
1284       case 0x1:
1285       {
1286         if((insn.bits & 0x1ffff) == 0x180d3)
1287         {
1288           #include "insns/fmin_d.h"
1289           break;
1290         }
1291         if((insn.bits & 0x3ff1ff) == 0xc0d3)
1292         {
1293           #include "insns/fcvt_d_l.h"
1294           break;
1295         }
1296         if((insn.bits & 0x3fffff) == 0xe0d3)
1297         {
1298           #include "insns/fcvt_d_w.h"
1299           break;
1300         }
1301         if((insn.bits & 0x3fffff) == 0x100d3)
1302         {
1303           #include "insns/fcvt_d_s.h"
1304           break;
1305         }
1306         if((insn.bits & 0x1ffff) == 0x190d3)
1307         {
1308           #include "insns/fmax_d.h"
1309           break;
1310         }
1311         if((insn.bits & 0x7c1ffff) == 0x1c0d3)
1312         {
1313           #include "insns/mftx_d.h"
1314           break;
1315         }
1316         if((insn.bits & 0x1ffff) == 0x170d3)
1317         {
1318           #include "insns/fle_d.h"
1319           break;
1320         }
1321         if((insn.bits & 0x1ffff) == 0x160d3)
1322         {
1323           #include "insns/flt_d.h"
1324           break;
1325         }
1326         if((insn.bits & 0x1f1ff) == 0x20d3)
1327         {
1328           #include "insns/fmul_d.h"
1329           break;
1330         }
1331         if((insn.bits & 0x1ffff) == 0x70d3)
1332         {
1333           #include "insns/fsgnjx_d.h"
1334           break;
1335         }
1336         if((insn.bits & 0x1ffff) == 0x150d3)
1337         {
1338           #include "insns/feq_d.h"
1339           break;
1340         }
1341         if((insn.bits & 0x3fffff) == 0xf0d3)
1342         {
1343           #include "insns/fcvt_d_wu.h"
1344           break;
1345         }
1346         if((insn.bits & 0x3ff1ff) == 0xb0d3)
1347         {
1348           #include "insns/fcvt_wu_d.h"
1349           break;
1350         }
1351         if((insn.bits & 0x1ffff) == 0x60d3)
1352         {
1353           #include "insns/fsgnjn_d.h"
1354           break;
1355         }
1356         if((insn.bits & 0x3ff1ff) == 0xd0d3)
1357         {
1358           #include "insns/fcvt_d_lu.h"
1359           break;
1360         }
1361         if((insn.bits & 0x3ff1ff) == 0xa0d3)
1362         {
1363           #include "insns/fcvt_w_d.h"
1364           break;
1365         }
1366         if((insn.bits & 0x3fffff) == 0x1e0d3)
1367         {
1368           #include "insns/mxtf_d.h"
1369           break;
1370         }
1371         if((insn.bits & 0x1ffff) == 0x50d3)
1372         {
1373           #include "insns/fsgnj_d.h"
1374           break;
1375         }
1376         if((insn.bits & 0x3ff1ff) == 0x80d3)
1377         {
1378           #include "insns/fcvt_l_d.h"
1379           break;
1380         }
1381         if((insn.bits & 0x1f1ff) == 0xd3)
1382         {
1383           #include "insns/fadd_d.h"
1384           break;
1385         }
1386         if((insn.bits & 0x3ff1ff) == 0x90d3)
1387         {
1388           #include "insns/fcvt_lu_d.h"
1389           break;
1390         }
1391         if((insn.bits & 0x1f1ff) == 0x10d3)
1392         {
1393           #include "insns/fsub_d.h"
1394           break;
1395         }
1396         if((insn.bits & 0x3ff1ff) == 0x40d3)
1397         {
1398           #include "insns/fsqrt_d.h"
1399           break;
1400         }
1401         if((insn.bits & 0x1f1ff) == 0x30d3)
1402         {
1403           #include "insns/fdiv_d.h"
1404           break;
1405         }
1406         throw trap_illegal_instruction;
1407       }
1408       case 0x4:
1409       {
1410         if((insn.bits & 0x3ff1ff) == 0x9053)
1411         {
1412           #include "insns/fcvt_lu_s.h"
1413           break;
1414         }
1415         if((insn.bits & 0x3ff1ff) == 0x11053)
1416         {
1417           #include "insns/fcvt_s_d.h"
1418           break;
1419         }
1420         if((insn.bits & 0x3ff1ff) == 0xe053)
1421         {
1422           #include "insns/fcvt_s_w.h"
1423           break;
1424         }
1425         if((insn.bits & 0x3ff1ff) == 0x8053)
1426         {
1427           #include "insns/fcvt_l_s.h"
1428           break;
1429         }
1430         if((insn.bits & 0x1f1ff) == 0x3053)
1431         {
1432           #include "insns/fdiv_s.h"
1433           break;
1434         }
1435         if((insn.bits & 0x3ff1ff) == 0xd053)
1436         {
1437           #include "insns/fcvt_s_lu.h"
1438           break;
1439         }
1440         if((insn.bits & 0x1f1ff) == 0x2053)
1441         {
1442           #include "insns/fmul_s.h"
1443           break;
1444         }
1445         if((insn.bits & 0x3ff1ff) == 0xb053)
1446         {
1447           #include "insns/fcvt_wu_s.h"
1448           break;
1449         }
1450         if((insn.bits & 0x3ff1ff) == 0xa053)
1451         {
1452           #include "insns/fcvt_w_s.h"
1453           break;
1454         }
1455         if((insn.bits & 0x1f1ff) == 0x1053)
1456         {
1457           #include "insns/fsub_s.h"
1458           break;
1459         }
1460         if((insn.bits & 0x3ff1ff) == 0xf053)
1461         {
1462           #include "insns/fcvt_s_wu.h"
1463           break;
1464         }
1465         if((insn.bits & 0x3ff1ff) == 0xc053)
1466         {
1467           #include "insns/fcvt_s_l.h"
1468           break;
1469         }
1470         if((insn.bits & 0x3ff1ff) == 0x4053)
1471         {
1472           #include "insns/fsqrt_s.h"
1473           break;
1474         }
1475         if((insn.bits & 0x1f1ff) == 0x53)
1476         {
1477           #include "insns/fadd_s.h"
1478           break;
1479         }
1480         throw trap_illegal_instruction;
1481       }
1482       case 0x5:
1483       {
1484         if((insn.bits & 0x3ff1ff) == 0xc0d3)
1485         {
1486           #include "insns/fcvt_d_l.h"
1487           break;
1488         }
1489         if((insn.bits & 0x1f1ff) == 0x20d3)
1490         {
1491           #include "insns/fmul_d.h"
1492           break;
1493         }
1494         if((insn.bits & 0x3ff1ff) == 0xb0d3)
1495         {
1496           #include "insns/fcvt_wu_d.h"
1497           break;
1498         }
1499         if((insn.bits & 0x3ff1ff) == 0xd0d3)
1500         {
1501           #include "insns/fcvt_d_lu.h"
1502           break;
1503         }
1504         if((insn.bits & 0x3ff1ff) == 0xa0d3)
1505         {
1506           #include "insns/fcvt_w_d.h"
1507           break;
1508         }
1509         if((insn.bits & 0x3ff1ff) == 0x80d3)
1510         {
1511           #include "insns/fcvt_l_d.h"
1512           break;
1513         }
1514         if((insn.bits & 0x1f1ff) == 0xd3)
1515         {
1516           #include "insns/fadd_d.h"
1517           break;
1518         }
1519         if((insn.bits & 0x3ff1ff) == 0x90d3)
1520         {
1521           #include "insns/fcvt_lu_d.h"
1522           break;
1523         }
1524         if((insn.bits & 0x1f1ff) == 0x10d3)
1525         {
1526           #include "insns/fsub_d.h"
1527           break;
1528         }
1529         if((insn.bits & 0x3ff1ff) == 0x40d3)
1530         {
1531           #include "insns/fsqrt_d.h"
1532           break;
1533         }
1534         if((insn.bits & 0x1f1ff) == 0x30d3)
1535         {
1536           #include "insns/fdiv_d.h"
1537           break;
1538         }
1539         throw trap_illegal_instruction;
1540       }
1541       default:
1542       {
1543         throw trap_illegal_instruction;
1544       }
1545     }
1546     break;
1547   }
1548   case 0x60:
1549   {
1550     #include "insns/c_addi.h"
1551     break;
1552   }
1553   case 0x63:
1554   {
1555     switch((insn.bits >> 0x7) & 0x7)
1556     {
1557       case 0x0:
1558       {
1559         #include "insns/beq.h"
1560         break;
1561       }
1562       case 0x1:
1563       {
1564         #include "insns/bne.h"
1565         break;
1566       }
1567       case 0x4:
1568       {
1569         #include "insns/blt.h"
1570         break;
1571       }
1572       case 0x5:
1573       {
1574         #include "insns/bge.h"
1575         break;
1576       }
1577       case 0x6:
1578       {
1579         #include "insns/bltu.h"
1580         break;
1581       }
1582       case 0x7:
1583       {
1584         #include "insns/bgeu.h"
1585         break;
1586       }
1587       default:
1588       {
1589         throw trap_illegal_instruction;
1590       }
1591     }
1592     break;
1593   }
1594   case 0x67:
1595   {
1596     #include "insns/j.h"
1597     break;
1598   }
1599   case 0x6b:
1600   {
1601     switch((insn.bits >> 0x7) & 0x7)
1602     {
1603       case 0x0:
1604       {
1605         #include "insns/jalr_c.h"
1606         break;
1607       }
1608       case 0x1:
1609       {
1610         #include "insns/jalr_r.h"
1611         break;
1612       }
1613       case 0x2:
1614       {
1615         #include "insns/jalr_j.h"
1616         break;
1617       }
1618       case 0x4:
1619       {
1620         if((insn.bits & 0x7ffffff) == 0x26b)
1621         {
1622           #include "insns/rdnpc.h"
1623           break;
1624         }
1625         throw trap_illegal_instruction;
1626       }
1627       default:
1628       {
1629         throw trap_illegal_instruction;
1630       }
1631     }
1632     break;
1633   }
1634   case 0x6f:
1635   {
1636     #include "insns/jal.h"
1637     break;
1638   }
1639   case 0x73:
1640   {
1641     switch((insn.bits >> 0x7) & 0x7)
1642     {
1643       case 0x0:
1644       {
1645         #include "insns/vcfgivl.h"
1646         break;
1647       }
1648       case 0x1:
1649       {
1650         if((insn.bits & 0x3fffff) == 0xf3)
1651         {
1652           #include "insns/setvl.h"
1653           break;
1654         }
1655         throw trap_illegal_instruction;
1656       }
1657       case 0x2:
1658       {
1659         if((insn.bits & 0xf80003ff) == 0x173)
1660         {
1661           #include "insns/vf.h"
1662           break;
1663         }
1664         throw trap_illegal_instruction;
1665       }
1666       default:
1667       {
1668         throw trap_illegal_instruction;
1669       }
1670     }
1671     break;
1672   }
1673   case 0x77:
1674   {
1675     switch((insn.bits >> 0x7) & 0x7)
1676     {
1677       case 0x0:
1678       {
1679         if((insn.bits & 0xffffffff) == 0x77)
1680         {
1681           #include "insns/syscall.h"
1682           break;
1683         }
1684         throw trap_illegal_instruction;
1685       }
1686       case 0x1:
1687       {
1688         if((insn.bits & 0xffffffff) == 0xf7)
1689         {
1690           #include "insns/break.h"
1691           break;
1692         }
1693         throw trap_illegal_instruction;
1694       }
1695       case 0x2:
1696       {
1697         if((insn.bits & 0xffffffff) == 0x177)
1698         {
1699           #include "insns/stop.h"
1700           break;
1701         }
1702         throw trap_illegal_instruction;
1703       }
1704       case 0x3:
1705       {
1706         if((insn.bits & 0x7ffffff) == 0x1f7)
1707         {
1708           #include "insns/utidx.h"
1709           break;
1710         }
1711         throw trap_illegal_instruction;
1712       }
1713       default:
1714       {
1715         throw trap_illegal_instruction;
1716       }
1717     }
1718     break;
1719   }
1720   case 0x7b:
1721   {
1722     switch((insn.bits >> 0x7) & 0x7)
1723     {
1724       case 0x0:
1725       {
1726         if((insn.bits & 0x7ffffff) == 0x7b)
1727         {
1728           #include "insns/ei.h"
1729           break;
1730         }
1731         throw trap_illegal_instruction;
1732       }
1733       case 0x1:
1734       {
1735         if((insn.bits & 0x7ffffff) == 0xfb)
1736         {
1737           #include "insns/di.h"
1738           break;
1739         }
1740         throw trap_illegal_instruction;
1741       }
1742       case 0x2:
1743       {
1744         if((insn.bits & 0x7c1ffff) == 0x17b)
1745         {
1746           #include "insns/mfpcr.h"
1747           break;
1748         }
1749         throw trap_illegal_instruction;
1750       }
1751       case 0x3:
1752       {
1753         if((insn.bits & 0xf801ffff) == 0x1fb)
1754         {
1755           #include "insns/mtpcr.h"
1756           break;
1757         }
1758         throw trap_illegal_instruction;
1759       }
1760       case 0x4:
1761       {
1762         if((insn.bits & 0xffffffff) == 0x27b)
1763         {
1764           #include "insns/eret.h"
1765           break;
1766         }
1767         throw trap_illegal_instruction;
1768       }
1769       default:
1770       {
1771         throw trap_illegal_instruction;
1772       }
1773     }
1774     break;
1775   }
1776   default:
1777   {
1778     throw trap_illegal_instruction;
1779   }
1780 }