Add writable ibuf and data registers.
[riscv-isa-sim.git] / riscv / extension.cc
1 // See LICENSE for license details.
2
3 #include "extension.h"
4 #include "trap.h"
5
6 extension_t::~extension_t()
7 {
8 }
9
10 void extension_t::illegal_instruction()
11 {
12 throw trap_illegal_instruction();
13 }
14
15 void extension_t::raise_interrupt()
16 {
17 reg_t prv = p->get_state()->prv;
18 reg_t mie = get_field(p->get_state()->mstatus, MSTATUS_MIE);
19
20 if (prv < PRV_M || (prv == PRV_M && mie))
21 p->raise_interrupt(IRQ_COP);
22
23 throw std::logic_error("a COP exception was posted, but interrupts are disabled!");
24 }
25
26 void extension_t::clear_interrupt()
27 {
28 }