riscv/gdbserver.cc

   1 #include <arpa/inet.h>
   2 #include <errno.h>
   3 #include <fcntl.h>
   4 #include <stdlib.h>
   5 #include <string.h>
   6 #include <sys/socket.h>
   7 #include <sys/types.h>
   8 #include <unistd.h>
   9
  10 #include <algorithm>
  11 #include <cassert>
  12 #include <cstdio>
  13 #include <vector>
  14
  15 #include "disasm.h"
  16 #include "sim.h"
  17 #include "gdbserver.h"
  18 #include "mmu.h"
  19
  20 #define C_EBREAK        0x9002
  21 #define EBREAK          0x00100073
  22
  23 //////////////////////////////////////// Utility Functions
  24
  25 #undef DEBUG
  26 #ifdef DEBUG
  27 #  define D(x) x
  28 #else
  29 #  define D(x)
  30 #endif // DEBUG
  31
  32 void die(const char* msg)
  33 {
  34   fprintf(stderr, "gdbserver code died: %s\n", msg);
  35   abort();
  36 }
  37
  38 // gdb's register list is defined in riscv_gdb_reg_names gdb/riscv-tdep.c in
  39 // its source tree. We must interpret the numbers the same here.
  40 enum {
  41   REG_XPR0 = 0,
  42   REG_XPR31 = 31,
  43   REG_PC = 32,
  44   REG_FPR0 = 33,
  45   REG_FPR31 = 64,
  46   REG_CSR0 = 65,
  47   REG_CSR4095 = 4160,
  48   REG_PRIV = 4161
  49 };
  50
  51 //////////////////////////////////////// Functions to generate RISC-V opcodes.
  52
  53 // TODO: Does this already exist somewhere?
  54
  55 #define ZERO    0
  56 // Using regnames.cc as source. The RVG Calling Convention of the 2.0 RISC-V
  57 // spec says it should be 2 and 3.
  58 #define S0      8
  59 #define S1      9
  60 static uint32_t bits(uint32_t value, unsigned int hi, unsigned int lo) {
  61   return (value >> lo) & ((1 << (hi+1-lo)) - 1);
  62 }
  63
  64 static uint32_t bit(uint32_t value, unsigned int b) {
  65   return (value >> b) & 1;
  66 }
  67
  68 static uint32_t jal(unsigned int rd, uint32_t imm) {
  69   return (bit(imm, 20) << 31) |
  70     (bits(imm, 10, 1) << 21) |
  71     (bit(imm, 11) << 20) |
  72     (bits(imm, 19, 12) << 12) |
  73     (rd << 7) |
  74     MATCH_JAL;
  75 }
  76
  77 static uint32_t csrsi(unsigned int csr, uint16_t imm) {
  78   return (csr << 20) |
  79     (bits(imm, 4, 0) << 15) |
  80     MATCH_CSRRSI;
  81 }
  82
  83 static uint32_t csrci(unsigned int csr, uint16_t imm) {
  84   return (csr << 20) |
  85     (bits(imm, 4, 0) << 15) |
  86     MATCH_CSRRCI;
  87 }
  88
  89 static uint32_t csrr(unsigned int rd, unsigned int csr) {
  90   return (csr << 20) | (rd << 7) | MATCH_CSRRS;
  91 }
  92
  93 static uint32_t csrw(unsigned int source, unsigned int csr) {
  94   return (csr << 20) | (source << 15) | MATCH_CSRRW;
  95 }
  96
  97 static uint32_t fence_i()
  98 {
  99   return MATCH_FENCE_I;
 100 }
 101
 102 static uint32_t sb(unsigned int src, unsigned int base, uint16_t offset)
 103 {
 104   return (bits(offset, 11, 5) << 25) |
 105     (src << 20) |
 106     (base << 15) |
 107     (bits(offset, 4, 0) << 7) |
 108     MATCH_SB;
 109 }
 110
 111 static uint32_t sh(unsigned int src, unsigned int base, uint16_t offset)
 112 {
 113   return (bits(offset, 11, 5) << 25) |
 114     (src << 20) |
 115     (base << 15) |
 116     (bits(offset, 4, 0) << 7) |
 117     MATCH_SH;
 118 }
 119
 120 static uint32_t sw(unsigned int src, unsigned int base, uint16_t offset)
 121 {
 122   return (bits(offset, 11, 5) << 25) |
 123     (src << 20) |
 124     (base << 15) |
 125     (bits(offset, 4, 0) << 7) |
 126     MATCH_SW;
 127 }
 128
 129 static uint32_t sd(unsigned int src, unsigned int base, uint16_t offset)
 130 {
 131   return (bits(offset, 11, 5) << 25) |
 132     (bits(src, 4, 0) << 20) |
 133     (base << 15) |
 134     (bits(offset, 4, 0) << 7) |
 135     MATCH_SD;
 136 }
 137
 138 static uint32_t sq(unsigned int src, unsigned int base, uint16_t offset)
 139 {
 140 #if 0
 141   return (bits(offset, 11, 5) << 25) |
 142     (bits(src, 4, 0) << 20) |
 143     (base << 15) |
 144     (bits(offset, 4, 0) << 7) |
 145     MATCH_SQ;
 146 #else
 147   abort();
 148 #endif
 149 }
 150
 151 static uint32_t lq(unsigned int rd, unsigned int base, uint16_t offset)
 152 {
 153 #if 0
 154   return (bits(offset, 11, 0) << 20) |
 155     (base << 15) |
 156     (bits(rd, 4, 0) << 7) |
 157     MATCH_LQ;
 158 #else
 159   abort();
 160 #endif
 161 }
 162
 163 static uint32_t ld(unsigned int rd, unsigned int base, uint16_t offset)
 164 {
 165   return (bits(offset, 11, 0) << 20) |
 166     (base << 15) |
 167     (bits(rd, 4, 0) << 7) |
 168     MATCH_LD;
 169 }
 170
 171 static uint32_t lw(unsigned int rd, unsigned int base, uint16_t offset)
 172 {
 173   return (bits(offset, 11, 0) << 20) |
 174     (base << 15) |
 175     (bits(rd, 4, 0) << 7) |
 176     MATCH_LW;
 177 }
 178
 179 static uint32_t lh(unsigned int rd, unsigned int base, uint16_t offset)
 180 {
 181   return (bits(offset, 11, 0) << 20) |
 182     (base << 15) |
 183     (bits(rd, 4, 0) << 7) |
 184     MATCH_LH;
 185 }
 186
 187 static uint32_t lb(unsigned int rd, unsigned int base, uint16_t offset)
 188 {
 189   return (bits(offset, 11, 0) << 20) |
 190     (base << 15) |
 191     (bits(rd, 4, 0) << 7) |
 192     MATCH_LB;
 193 }
 194
 195 static uint32_t fsw(unsigned int src, unsigned int base, uint16_t offset)
 196 {
 197   return (bits(offset, 11, 5) << 25) |
 198     (bits(src, 4, 0) << 20) |
 199     (base << 15) |
 200     (bits(offset, 4, 0) << 7) |
 201     MATCH_FSW;
 202 }
 203
 204 static uint32_t fsd(unsigned int src, unsigned int base, uint16_t offset)
 205 {
 206   return (bits(offset, 11, 5) << 25) |
 207     (bits(src, 4, 0) << 20) |
 208     (base << 15) |
 209     (bits(offset, 4, 0) << 7) |
 210     MATCH_FSD;
 211 }
 212
 213 static uint32_t flw(unsigned int src, unsigned int base, uint16_t offset)
 214 {
 215   return (bits(offset, 11, 5) << 25) |
 216     (bits(src, 4, 0) << 20) |
 217     (base << 15) |
 218     (bits(offset, 4, 0) << 7) |
 219     MATCH_FLW;
 220 }
 221
 222 static uint32_t fld(unsigned int src, unsigned int base, uint16_t offset)
 223 {
 224   return (bits(offset, 11, 5) << 25) |
 225     (bits(src, 4, 0) << 20) |
 226     (base << 15) |
 227     (bits(offset, 4, 0) << 7) |
 228     MATCH_FLD;
 229 }
 230
 231 static uint32_t addi(unsigned int dest, unsigned int src, uint16_t imm)
 232 {
 233   return (bits(imm, 11, 0) << 20) |
 234     (src << 15) |
 235     (dest << 7) |
 236     MATCH_ADDI;
 237 }
 238
 239 static uint32_t ori(unsigned int dest, unsigned int src, uint16_t imm)
 240 {
 241   return (bits(imm, 11, 0) << 20) |
 242     (src << 15) |
 243     (dest << 7) |
 244     MATCH_ORI;
 245 }
 246
 247 static uint32_t xori(unsigned int dest, unsigned int src, uint16_t imm)
 248 {
 249   return (bits(imm, 11, 0) << 20) |
 250     (src << 15) |
 251     (dest << 7) |
 252     MATCH_XORI;
 253 }
 254
 255 static uint32_t srli(unsigned int dest, unsigned int src, uint8_t shamt)
 256 {
 257   return (bits(shamt, 4, 0) << 20) |
 258     (src << 15) |
 259     (dest << 7) |
 260     MATCH_SRLI;
 261 }
 262
 263
 264 static uint32_t nop()
 265 {
 266   return addi(0, 0, 0);
 267 }
 268
 269 template <typename T>
 270 unsigned int circular_buffer_t<T>::size() const
 271 {
 272   if (end >= start)
 273     return end - start;
 274   else
 275     return end + capacity - start;
 276 }
 277
 278 template <typename T>
 279 void circular_buffer_t<T>::consume(unsigned int bytes)
 280 {
 281   start = (start + bytes) % capacity;
 282 }
 283
 284 template <typename T>
 285 unsigned int circular_buffer_t<T>::contiguous_empty_size() const
 286 {
 287   if (end >= start)
 288     if (start == 0)
 289       return capacity - end - 1;
 290     else
 291       return capacity - end;
 292   else
 293     return start - end - 1;
 294 }
 295
 296 template <typename T>
 297 unsigned int circular_buffer_t<T>::contiguous_data_size() const
 298 {
 299   if (end >= start)
 300     return end - start;
 301   else
 302     return capacity - start;
 303 }
 304
 305 template <typename T>
 306 void circular_buffer_t<T>::data_added(unsigned int bytes)
 307 {
 308   end += bytes;
 309   assert(end <= capacity);
 310   if (end == capacity)
 311     end = 0;
 312 }
 313
 314 template <typename T>
 315 void circular_buffer_t<T>::reset()
 316 {
 317   start = 0;
 318   end = 0;
 319 }
 320
 321 template <typename T>
 322 void circular_buffer_t<T>::append(const T *src, unsigned int count)
 323 {
 324   unsigned int copy = std::min(count, contiguous_empty_size());
 325   memcpy(contiguous_empty(), src, copy * sizeof(T));
 326   data_added(copy);
 327   count -= copy;
 328   if (count > 0) {
 329     assert(count < contiguous_empty_size());
 330     memcpy(contiguous_empty(), src, count * sizeof(T));
 331     data_added(count);
 332   }
 333 }
 334
 335 ////////////////////////////// Debug Operations
 336
 337 class halt_op_t : public operation_t
 338 {
 339   public:
 340     halt_op_t(gdbserver_t& gdbserver, bool send_status=false) :
 341       operation_t(gdbserver), send_status(send_status),
 342       state(ST_ENTER) {};
 343
 344     void write_dpc_program() {
 345       gs.dr_write32(0, csrsi(CSR_DCSR, DCSR_HALT));
 346       gs.dr_write32(1, csrr(S0, CSR_DPC));
 347       gs.dr_write_store(2, S0, SLOT_DATA0);
 348       gs.dr_write_jump(3);
 349       gs.set_interrupt(0);
 350     }
 351
 352     bool perform_step(unsigned int step) {
 353       switch (state) {
 354         case ST_ENTER:
 355           if (gs.xlen == 0) {
 356             gs.dr_write32(0, xori(S1, ZERO, -1));
 357             gs.dr_write32(1, srli(S1, S1, 31));
 358             // 0x00000001  0x00000001:ffffffff  0x00000001:ffffffff:ffffffff:ffffffff
 359             gs.dr_write32(2, sw(S1, ZERO, DEBUG_RAM_START));
 360             gs.dr_write32(3, srli(S1, S1, 31));
 361             // 0x00000000  0x00000000:00000003  0x00000000:00000003:ffffffff:ffffffff
 362             gs.dr_write32(4, sw(S1, ZERO, DEBUG_RAM_START + 4));
 363             gs.dr_write_jump(5);
 364             gs.set_interrupt(0);
 365             state = ST_XLEN;
 366
 367           } else {
 368             write_dpc_program();
 369             state = ST_DPC;
 370           }
 371           return false;
 372
 373         case ST_XLEN:
 374           {
 375             uint32_t word0 = gs.dr_read32(0);
 376             uint32_t word1 = gs.dr_read32(1);
 377
 378             if (word0 == 1 && word1 == 0) {
 379               gs.xlen = 32;
 380             } else if (word0 == 0xffffffff && word1 == 3) {
 381               gs.xlen = 64;
 382             } else if (word0 == 0xffffffff && word1 == 0xffffffff) {
 383               gs.xlen = 128;
 384             }
 385
 386             write_dpc_program();
 387             state = ST_DPC;
 388             return false;
 389           }
 390
 391         case ST_DPC:
 392           gs.dpc = gs.dr_read(SLOT_DATA0);
 393           gs.dr_write32(0, csrr(S0, CSR_MSTATUS));
 394           gs.dr_write_store(1, S0, SLOT_DATA0);
 395           gs.dr_write_jump(2);
 396           gs.set_interrupt(0);
 397           state = ST_MSTATUS;
 398           return false;
 399
 400         case ST_MSTATUS:
 401           gs.mstatus = gs.dr_read(SLOT_DATA0);
 402           gs.dr_write32(0, csrr(S0, CSR_DCSR));
 403           gs.dr_write32(1, sw(S0, 0, (uint16_t) DEBUG_RAM_START + 16));
 404           gs.dr_write_jump(2);
 405           gs.set_interrupt(0);
 406           state = ST_DCSR;
 407           return false;
 408
 409         case ST_DCSR:
 410           gs.dcsr = gs.dr_read32(4);
 411
 412           gs.sptbr_valid = false;
 413           gs.pte_cache.clear();
 414
 415           if (send_status) {
 416             switch (get_field(gs.dcsr, DCSR_CAUSE)) {
 417               case DCSR_CAUSE_NONE:
 418                 fprintf(stderr, "Internal error. Processor halted without reason.\n");
 419                 abort();
 420
 421               case DCSR_CAUSE_DEBUGINT:
 422                 gs.send_packet("S02");   // Pretend program received SIGINT.
 423                 break;
 424
 425               case DCSR_CAUSE_HWBP:
 426               case DCSR_CAUSE_STEP:
 427               case DCSR_CAUSE_HALT:
 428                 // There's no gdb code for this.
 429                 gs.send_packet("T05");
 430                 break;
 431               case DCSR_CAUSE_SWBP:
 432                 gs.send_packet("T05swbreak:;");
 433                 break;
 434             }
 435           }
 436           return true;
 437
 438         default:
 439           assert(0);
 440       }
 441     }
 442
 443   private:
 444     bool send_status;
 445     enum {
 446       ST_ENTER,
 447       ST_XLEN,
 448       ST_DPC,
 449       ST_MSTATUS,
 450       ST_DCSR
 451     } state;
 452 };
 453
 454 class continue_op_t : public operation_t
 455 {
 456   public:
 457     continue_op_t(gdbserver_t& gdbserver, bool single_step) :
 458       operation_t(gdbserver), single_step(single_step) {};
 459
 460     bool perform_step(unsigned int step) {
 461       switch (step) {
 462         case 0:
 463           gs.dr_write_load(0, S0, SLOT_DATA0);
 464           gs.dr_write32(1, csrw(S0, CSR_DPC));
 465           // TODO: Isn't there a fence.i in Debug ROM already?
 466           if (gs.fence_i_required) {
 467             gs.dr_write32(2, fence_i());
 468             gs.dr_write_jump(3);
 469             gs.fence_i_required = false;
 470           } else {
 471             gs.dr_write_jump(2);
 472           }
 473           gs.dr_write(SLOT_DATA0, gs.dpc);
 474           gs.set_interrupt(0);
 475           return false;
 476
 477         case 1:
 478           gs.dr_write_load(0, S0, SLOT_DATA0);
 479           gs.dr_write32(1, csrw(S0, CSR_MSTATUS));
 480           gs.dr_write_jump(2);
 481           gs.dr_write(SLOT_DATA0, gs.mstatus);
 482           gs.set_interrupt(0);
 483           return false;
 484
 485         case 2:
 486           gs.dr_write32(0, lw(S0, 0, (uint16_t) DEBUG_RAM_START+16));
 487           gs.dr_write32(1, csrw(S0, CSR_DCSR));
 488           gs.dr_write_jump(2);
 489
 490           reg_t dcsr = set_field(gs.dcsr, DCSR_HALT, 0);
 491           dcsr = set_field(dcsr, DCSR_STEP, single_step);
 492           // Software breakpoints should go here.
 493           dcsr = set_field(dcsr, DCSR_EBREAKM, 1);
 494           dcsr = set_field(dcsr, DCSR_EBREAKH, 1);
 495           dcsr = set_field(dcsr, DCSR_EBREAKS, 1);
 496           dcsr = set_field(dcsr, DCSR_EBREAKU, 1);
 497           gs.dr_write32(4, dcsr);
 498
 499           gs.set_interrupt(0);
 500           return true;
 501       }
 502       return false;
 503     }
 504
 505   private:
 506     bool single_step;
 507 };
 508
 509 class general_registers_read_op_t : public operation_t
 510 {
 511   // Register order that gdb expects is:
 512   //   "x0",  "x1",  "x2",  "x3",  "x4",  "x5",  "x6",  "x7",
 513   //   "x8",  "x9",  "x10", "x11", "x12", "x13", "x14", "x15",
 514   //   "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
 515   //   "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31",
 516
 517   // Each byte of register data is described by two hex digits. The bytes with
 518   // the register are transmitted in target byte order. The size of each
 519   // register and their position within the ‘g’ packet are determined by the
 520   // gdb internal gdbarch functions DEPRECATED_REGISTER_RAW_SIZE and
 521   // gdbarch_register_name.
 522
 523   public:
 524     general_registers_read_op_t(gdbserver_t& gdbserver) :
 525       operation_t(gdbserver) {};
 526
 527     bool perform_step(unsigned int step)
 528     {
 529       D(fprintf(stderr, "register_read step %d\n", step));
 530       if (step == 0) {
 531         gs.start_packet();
 532
 533         // x0 is always zero.
 534         if (gs.xlen == 32) {
 535           gs.send((uint32_t) 0);
 536         } else {
 537           gs.send((uint64_t) 0);
 538         }
 539
 540         gs.dr_write_store(0, 1, SLOT_DATA0);
 541         gs.dr_write_store(1, 2, SLOT_DATA1);
 542         gs.dr_write_jump(2);
 543         gs.set_interrupt(0);
 544         return false;
 545       }
 546
 547       if (gs.xlen == 32) {
 548         gs.send((uint32_t) gs.dr_read(SLOT_DATA0));
 549       } else {
 550         gs.send((uint64_t) gs.dr_read(SLOT_DATA0));
 551       }
 552       if (step >= 16) {
 553         gs.end_packet();
 554         return true;
 555       }
 556
 557       if (gs.xlen == 32) {
 558         gs.send((uint32_t) gs.dr_read(SLOT_DATA1));
 559       } else {
 560         gs.send((uint64_t) gs.dr_read(SLOT_DATA1));
 561       }
 562
 563       unsigned int current_reg = 2 * step + 1;
 564       unsigned int i = 0;
 565       if (current_reg == S1) {
 566         gs.dr_write_load(i++, S1, SLOT_DATA_LAST);
 567       }
 568       gs.dr_write_store(i++, current_reg, SLOT_DATA0);
 569       if (current_reg + 1 == S0) {
 570         gs.dr_write32(i++, csrr(S0, CSR_DSCRATCH));
 571       }
 572       if (step < 15) {
 573         gs.dr_write_store(i++, current_reg+1, SLOT_DATA1);
 574       }
 575       gs.dr_write_jump(i);
 576       gs.set_interrupt(0);
 577
 578       return false;
 579     }
 580 };
 581
 582 class register_read_op_t : public operation_t
 583 {
 584   public:
 585     register_read_op_t(gdbserver_t& gdbserver, unsigned int reg) :
 586       operation_t(gdbserver), reg(reg) {};
 587
 588     bool perform_step(unsigned int step)
 589     {
 590       switch (step) {
 591         case 0:
 592           if (reg >= REG_XPR0 && reg <= REG_XPR31) {
 593             die("handle_register_read");
 594             // send(p->state.XPR[reg - REG_XPR0]);
 595           } else if (reg == REG_PC) {
 596             gs.start_packet();
 597             if (gs.xlen == 32) {
 598               gs.send((uint32_t) gs.dpc);
 599             } else {
 600               gs.send(gs.dpc);
 601             }
 602             gs.end_packet();
 603             return true;
 604           } else if (reg >= REG_FPR0 && reg <= REG_FPR31) {
 605             // send(p->state.FPR[reg - REG_FPR0]);
 606             if (gs.xlen == 32) {
 607               gs.dr_write32(0, fsw(reg - REG_FPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
 608             } else {
 609               gs.dr_write32(0, fsd(reg - REG_FPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
 610             }
 611             gs.dr_write_jump(1);
 612           } else if (reg >= REG_CSR0 && reg <= REG_CSR4095) {
 613             gs.dr_write32(0, csrr(S0, reg - REG_CSR0));
 614             gs.dr_write_store(1, S0, SLOT_DATA0);
 615             gs.dr_write_jump(2);
 616             // If we hit an exception reading the CSR, we'll end up returning ~0 as
 617             // the register's value, which is what we want. (Right?)
 618             gs.dr_write(SLOT_DATA0, ~(uint64_t) 0);
 619           } else if (reg == REG_PRIV) {
 620             gs.start_packet();
 621             gs.send((uint8_t) get_field(gs.dcsr, DCSR_PRV));
 622             gs.end_packet();
 623             return true;
 624           } else {
 625             gs.send_packet("E02");
 626             return true;
 627           }
 628           gs.set_interrupt(0);
 629           return false;
 630
 631         case 1:
 632           gs.start_packet();
 633           if (gs.xlen == 32) {
 634             gs.send(gs.dr_read32(4));
 635           } else {
 636             gs.send(gs.dr_read(SLOT_DATA0));
 637           }
 638           gs.end_packet();
 639           return true;
 640       }
 641       return false;
 642     }
 643
 644   private:
 645     unsigned int reg;
 646 };
 647
 648 class register_write_op_t : public operation_t
 649 {
 650   public:
 651     register_write_op_t(gdbserver_t& gdbserver, unsigned int reg, reg_t value) :
 652       operation_t(gdbserver), reg(reg), value(value) {};
 653
 654     bool perform_step(unsigned int step)
 655     {
 656       gs.dr_write_load(0, S0, SLOT_DATA0);
 657       gs.dr_write(SLOT_DATA0, value);
 658       if (reg == S0) {
 659         gs.dr_write32(1, csrw(S0, CSR_DSCRATCH));
 660         gs.dr_write_jump(2);
 661       } else if (reg == S1) {
 662         gs.dr_write_store(1, S0, SLOT_DATA_LAST);
 663         gs.dr_write_jump(2);
 664       } else if (reg >= REG_XPR0 && reg <= REG_XPR31) {
 665         gs.dr_write32(1, addi(reg, S0, 0));
 666         gs.dr_write_jump(2);
 667       } else if (reg == REG_PC) {
 668         gs.dpc = value;
 669         return true;
 670       } else if (reg >= REG_FPR0 && reg <= REG_FPR31) {
 671         if (gs.xlen == 32) {
 672           gs.dr_write32(0, flw(reg - REG_FPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
 673         } else {
 674           gs.dr_write32(0, fld(reg - REG_FPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
 675         }
 676         gs.dr_write_jump(1);
 677       } else if (reg >= REG_CSR0 && reg <= REG_CSR4095) {
 678         gs.dr_write32(1, csrw(S0, reg - REG_CSR0));
 679         gs.dr_write_jump(2);
 680         if (reg == REG_CSR0 + CSR_SPTBR) {
 681           gs.sptbr = value;
 682           gs.sptbr_valid = true;
 683         }
 684       } else if (reg == REG_PRIV) {
 685         gs.dcsr = set_field(gs.dcsr, DCSR_PRV, value);
 686         return true;
 687       } else {
 688         gs.send_packet("E02");
 689         return true;
 690       }
 691       gs.set_interrupt(0);
 692       gs.send_packet("OK");
 693       return true;
 694     }
 695
 696   private:
 697     unsigned int reg;
 698     reg_t value;
 699 };
 700
 701 class memory_read_op_t : public operation_t
 702 {
 703   public:
 704     // Read length bytes from vaddr, storing the result into data.
 705     // If data is NULL, send the result straight to gdb.
 706     memory_read_op_t(gdbserver_t& gdbserver, reg_t vaddr, unsigned int length,
 707         unsigned char *data=NULL) :
 708       operation_t(gdbserver), vaddr(vaddr), length(length), data(data) {};
 709
 710     bool perform_step(unsigned int step)
 711     {
 712       if (step == 0) {
 713         // address goes in S0
 714         paddr = gs.translate(vaddr);
 715         access_size = gs.find_access_size(paddr, length);
 716
 717         gs.dr_write_load(0, S0, SLOT_DATA0);
 718         switch (access_size) {
 719           case 1:
 720             gs.dr_write32(1, lb(S1, S0, 0));
 721             break;
 722           case 2:
 723             gs.dr_write32(1, lh(S1, S0, 0));
 724             break;
 725           case 4:
 726             gs.dr_write32(1, lw(S1, S0, 0));
 727             break;
 728           case 8:
 729             gs.dr_write32(1, ld(S1, S0, 0));
 730             break;
 731         }
 732         gs.dr_write_store(2, S1, SLOT_DATA1);
 733         gs.dr_write_jump(3);
 734         gs.dr_write(SLOT_DATA0, paddr);
 735         gs.set_interrupt(0);
 736
 737         if (!data) {
 738           gs.start_packet();
 739         }
 740         return false;
 741       }
 742
 743       char buffer[3];
 744       reg_t value = gs.dr_read(SLOT_DATA1);
 745       for (unsigned int i = 0; i < access_size; i++) {
 746         if (data) {
 747           *(data++) = value & 0xff;
 748           D(fprintf(stderr, "%02x", (unsigned int) (value & 0xff)));
 749         } else {
 750           sprintf(buffer, "%02x", (unsigned int) (value & 0xff));
 751           gs.send(buffer);
 752         }
 753         value >>= 8;
 754       }
 755       if (data) {
 756         D(fprintf(stderr, "\n"));
 757       }
 758       length -= access_size;
 759       paddr += access_size;
 760
 761       if (length == 0) {
 762         if (!data) {
 763           gs.end_packet();
 764         }
 765         return true;
 766       } else {
 767         gs.dr_write(SLOT_DATA0, paddr);
 768         gs.set_interrupt(0);
 769         return false;
 770       }
 771     }
 772
 773   private:
 774     reg_t vaddr;
 775     unsigned int length;
 776     unsigned char* data;
 777     reg_t paddr;
 778     unsigned int access_size;
 779 };
 780
 781 class memory_write_op_t : public operation_t
 782 {
 783   public:
 784     memory_write_op_t(gdbserver_t& gdbserver, reg_t vaddr, unsigned int length,
 785         const unsigned char *data) :
 786       operation_t(gdbserver), vaddr(vaddr), offset(0), length(length), data(data) {};
 787
 788     ~memory_write_op_t() {
 789       delete[] data;
 790     }
 791
 792     bool perform_step(unsigned int step)
 793     {
 794       reg_t paddr = gs.translate(vaddr);
 795
 796       unsigned int data_offset;
 797       switch (gs.xlen) {
 798         case 32:
 799           data_offset = slot_offset32[SLOT_DATA1];
 800           break;
 801         case 64:
 802           data_offset = slot_offset64[SLOT_DATA1];
 803           break;
 804         case 128:
 805           data_offset = slot_offset128[SLOT_DATA1];
 806           break;
 807         default:
 808           abort();
 809       }
 810
 811       if (step == 0) {
 812         access_size = gs.find_access_size(paddr, length);
 813
 814         D(fprintf(stderr, "write to 0x%lx -> 0x%lx (access=%d): ", vaddr, paddr,
 815             access_size));
 816         for (unsigned int i = 0; i < length; i++) {
 817           D(fprintf(stderr, "%02x", data[i]));
 818         }
 819         D(fprintf(stderr, "\n"));
 820
 821         // address goes in S0
 822         gs.dr_write_load(0, S0, SLOT_DATA0);
 823         switch (access_size) {
 824           case 1:
 825             gs.dr_write32(1, lb(S1, 0, (uint16_t) DEBUG_RAM_START + 4*data_offset));
 826             gs.dr_write32(2, sb(S1, S0, 0));
 827             gs.dr_write32(data_offset, data[0]);
 828             break;
 829           case 2:
 830             gs.dr_write32(1, lh(S1, 0, (uint16_t) DEBUG_RAM_START + 4*data_offset));
 831             gs.dr_write32(2, sh(S1, S0, 0));
 832             gs.dr_write32(data_offset, data[0] | (data[1] << 8));
 833             break;
 834           case 4:
 835             gs.dr_write32(1, lw(S1, 0, (uint16_t) DEBUG_RAM_START + 4*data_offset));
 836             gs.dr_write32(2, sw(S1, S0, 0));
 837             gs.dr_write32(data_offset, data[0] | (data[1] << 8) |
 838                 (data[2] << 16) | (data[3] << 24));
 839             break;
 840           case 8:
 841             gs.dr_write32(1, ld(S1, 0, (uint16_t) DEBUG_RAM_START + 4*data_offset));
 842             gs.dr_write32(2, sd(S1, S0, 0));
 843             gs.dr_write32(data_offset, data[0] | (data[1] << 8) |
 844                 (data[2] << 16) | (data[3] << 24));
 845             gs.dr_write32(data_offset+1, data[4] | (data[5] << 8) |
 846                 (data[6] << 16) | (data[7] << 24));
 847             break;
 848           default:
 849             fprintf(stderr, "gdbserver error: write %d bytes to 0x%lx -> 0x%lx; "
 850                 "access_size=%d\n", length, vaddr, paddr, access_size);
 851             gs.send_packet("E12");
 852             return true;
 853         }
 854         gs.dr_write_jump(3);
 855         gs.dr_write(SLOT_DATA0, paddr);
 856         gs.set_interrupt(0);
 857
 858         return false;
 859       }
 860
 861       if (gs.dr_read32(DEBUG_RAM_SIZE / 4 - 1)) {
 862         fprintf(stderr, "Exception happened while writing to 0x%lx -> 0x%lx\n",
 863             vaddr, paddr);
 864       }
 865
 866       offset += access_size;
 867       if (offset >= length) {
 868         gs.send_packet("OK");
 869         return true;
 870       } else {
 871         const unsigned char *d = data + offset;
 872         switch (access_size) {
 873           case 1:
 874             gs.dr_write32(data_offset, d[0]);
 875             break;
 876           case 2:
 877             gs.dr_write32(data_offset, d[0] | (d[1] << 8));
 878             break;
 879           case 4:
 880             gs.dr_write32(data_offset, d[0] | (d[1] << 8) |
 881                 (d[2] << 16) | (d[3] << 24));
 882             break;
 883           case 8:
 884             gs.dr_write32(data_offset, d[0] | (d[1] << 8) |
 885                 (d[2] << 16) | (d[3] << 24));
 886             gs.dr_write32(data_offset+1, d[4] | (d[5] << 8) |
 887                 (d[6] << 16) | (d[7] << 24));
 888             break;
 889           default:
 890             gs.send_packet("E13");
 891             return true;
 892         }
 893         gs.dr_write(SLOT_DATA0, paddr + offset);
 894         gs.set_interrupt(0);
 895         return false;
 896       }
 897     }
 898
 899   private:
 900     reg_t vaddr;
 901     unsigned int offset;
 902     unsigned int length;
 903     unsigned int access_size;
 904     const unsigned char *data;
 905 };
 906
 907 class collect_translation_info_op_t : public operation_t
 908 {
 909   public:
 910     // Read sufficient information from the target into gdbserver structures so
 911     // that it's possible to translate vaddr, vaddr+length, and all addresses
 912     // in between to physical addresses.
 913     collect_translation_info_op_t(gdbserver_t& gdbserver, reg_t vaddr, size_t length) :
 914       operation_t(gdbserver), state(STATE_START), vaddr(vaddr), length(length) {};
 915
 916     bool perform_step(unsigned int step)
 917     {
 918       unsigned int vm = gs.virtual_memory();
 919
 920       if (step == 0) {
 921         switch (vm) {
 922           case VM_MBARE:
 923             // Nothing to be done.
 924             return true;
 925
 926           case VM_SV32:
 927             levels = 2;
 928             ptidxbits = 10;
 929             ptesize = 4;
 930             break;
 931           case VM_SV39:
 932             levels = 3;
 933             ptidxbits = 9;
 934             ptesize = 8;
 935             break;
 936           case VM_SV48:
 937             levels = 4;
 938             ptidxbits = 9;
 939             ptesize = 8;
 940             break;
 941
 942           default:
 943             {
 944               char buf[100];
 945               sprintf(buf, "VM mode %d is not supported by gdbserver.cc.", vm);
 946               die(buf);
 947               return true;        // die doesn't return, but gcc doesn't know that.
 948             }
 949         }
 950       }
 951
 952       // Perform any reads from the just-completed action.
 953       switch (state) {
 954         case STATE_START:
 955           break;
 956         case STATE_READ_SPTBR:
 957           gs.sptbr = gs.dr_read(SLOT_DATA0);
 958           gs.sptbr_valid = true;
 959           break;
 960         case STATE_READ_PTE:
 961           if (ptesize == 4) {
 962               gs.pte_cache[pte_addr] = gs.dr_read32(4);
 963           } else {
 964               gs.pte_cache[pte_addr] = ((uint64_t) gs.dr_read32(5) << 32) |
 965                   gs.dr_read32(4);
 966           }
 967           D(fprintf(stderr, "pte_cache[0x%lx] = 0x%lx\n", pte_addr, gs.pte_cache[pte_addr]));
 968           break;
 969       }
 970
 971       // Set up the next action.
 972       // We only get here for VM_SV32/39/38.
 973
 974       if (!gs.sptbr_valid) {
 975         state = STATE_READ_SPTBR;
 976         gs.dr_write32(0, csrr(S0, CSR_SPTBR));
 977         gs.dr_write_store(1, S0, SLOT_DATA0);
 978         gs.dr_write_jump(2);
 979         gs.set_interrupt(0);
 980         return false;
 981       }
 982
 983       reg_t base = gs.sptbr << PGSHIFT;
 984       int ptshift = (levels - 1) * ptidxbits;
 985       for (unsigned int i = 0; i < levels; i++, ptshift -= ptidxbits) {
 986         reg_t idx = (vaddr >> (PGSHIFT + ptshift)) & ((1 << ptidxbits) - 1);
 987
 988         pte_addr = base + idx * ptesize;
 989         auto it = gs.pte_cache.find(pte_addr);
 990         if (it == gs.pte_cache.end()) {
 991           state = STATE_READ_PTE;
 992           if (ptesize == 4) {
 993             gs.dr_write32(0, lw(S0, 0, (uint16_t) DEBUG_RAM_START + 16));
 994             gs.dr_write32(1, lw(S1, S0, 0));
 995             gs.dr_write32(2, sw(S1, 0, (uint16_t) DEBUG_RAM_START + 16));
 996           } else {
 997             assert(gs.xlen >= 64);
 998             gs.dr_write32(0, ld(S0, 0, (uint16_t) DEBUG_RAM_START + 16));
 999             gs.dr_write32(1, ld(S1, S0, 0));
1000             gs.dr_write32(2, sd(S1, 0, (uint16_t) DEBUG_RAM_START + 16));
1001           }
1002           gs.dr_write32(3, jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*3))));
1003           gs.dr_write32(4, pte_addr);
1004           gs.dr_write32(5, pte_addr >> 32);
1005           gs.set_interrupt(0);
1006           return false;
1007         }
1008
1009         reg_t pte = gs.pte_cache[pte_addr];
1010         reg_t ppn = pte >> PTE_PPN_SHIFT;
1011
1012         if (PTE_TABLE(pte)) { // next level of page table
1013           base = ppn << PGSHIFT;
1014         } else {
1015           // We've collected all the data required for the translation.
1016           return true;
1017         }
1018       }
1019       fprintf(stderr,
1020           "ERROR: gdbserver couldn't find appropriate PTEs to translate 0x%lx\n",
1021           vaddr);
1022       return true;
1023     }
1024
1025   private:
1026     enum {
1027       STATE_START,
1028       STATE_READ_SPTBR,
1029       STATE_READ_PTE
1030     } state;
1031     reg_t vaddr;
1032     size_t length;
1033     unsigned int levels;
1034     unsigned int ptidxbits;
1035     unsigned int ptesize;
1036     reg_t pte_addr;
1037 };
1038
1039 class hardware_breakpoint_insert_op_t : public operation_t
1040 {
1041   public:
1042     hardware_breakpoint_insert_op_t(gdbserver_t& gdbserver,
1043         hardware_breakpoint_t bp) :
1044       operation_t(gdbserver), state(STATE_START), bp(bp) {};
1045
1046     void write_new_index_program()
1047     {
1048       gs.dr_write_load(0, S0, SLOT_DATA1);
1049       gs.dr_write32(1, csrw(S0, CSR_TSELECT));
1050       gs.dr_write32(2, csrr(S0, CSR_TSELECT));
1051       gs.dr_write_store(3, S0, SLOT_DATA1);
1052       gs.dr_write_jump(4);
1053       gs.dr_write(SLOT_DATA1, bp.index);
1054     }
1055
1056     bool perform_step(unsigned int step)
1057     {
1058       switch (state) {
1059         case STATE_START:
1060           bp.index = 0;
1061           write_new_index_program();
1062           state = STATE_CHECK_INDEX;
1063           break;
1064
1065         case STATE_CHECK_INDEX:
1066           if (gs.dr_read(SLOT_DATA1) != bp.index) {
1067             // We've exhausted breakpoints without finding an appropriate one.
1068             gs.send_packet("E58");
1069             return true;
1070           }
1071
1072           gs.dr_write32(0, csrr(S0, CSR_TDATA0));
1073           gs.dr_write_store(1, S0, SLOT_DATA0);
1074           gs.dr_write_jump(2);
1075           state = STATE_CHECK_MCONTROL;
1076           break;
1077
1078         case STATE_CHECK_MCONTROL:
1079           {
1080             reg_t mcontrol = gs.dr_read(SLOT_DATA0);
1081             unsigned int type = mcontrol >> (gs.xlen - 4);
1082             if (type == 0) {
1083               // We've exhausted breakpoints without finding an appropriate one.
1084               gs.send_packet("E58");
1085               return true;
1086             }
1087
1088             if (type == 2 &&
1089                 get_field(mcontrol, MCONTROL_ACTION) == MCONTROL_ACTION_NONE) {
1090               // Found an unused trigger.
1091               gs.dr_write_load(0, S0, SLOT_DATA1);
1092               gs.dr_write32(1, csrw(S0, CSR_TDATA0));
1093               gs.dr_write_jump(2);
1094               mcontrol = set_field(0, MCONTROL_ACTION, MCONTROL_ACTION_DEBUG_MODE);
1095               mcontrol = set_field(mcontrol, MCONTROL_MATCH, MCONTROL_MATCH_EQUAL);
1096               mcontrol = set_field(mcontrol, MCONTROL_M, 1);
1097               mcontrol = set_field(mcontrol, MCONTROL_H, 1);
1098               mcontrol = set_field(mcontrol, MCONTROL_S, 1);
1099               mcontrol = set_field(mcontrol, MCONTROL_U, 1);
1100               mcontrol = set_field(mcontrol, MCONTROL_EXECUTE, bp.execute);
1101               mcontrol = set_field(mcontrol, MCONTROL_LOAD, bp.load);
1102               mcontrol = set_field(mcontrol, MCONTROL_STORE, bp.store);
1103               gs.dr_write(SLOT_DATA1, mcontrol);
1104               state = STATE_WRITE_ADDRESS;
1105             } else {
1106               bp.index++;
1107               write_new_index_program();
1108               state = STATE_CHECK_INDEX;
1109             }
1110           }
1111           break;
1112
1113         case STATE_WRITE_ADDRESS:
1114           {
1115             gs.dr_write_load(0, S0, SLOT_DATA1);
1116             gs.dr_write32(1, csrw(S0, CSR_TDATA1));
1117             gs.dr_write_jump(2);
1118             gs.dr_write(SLOT_DATA1, bp.vaddr);
1119             gs.set_interrupt(0);
1120             gs.send_packet("OK");
1121
1122             gs.hardware_breakpoints.insert(bp);
1123
1124             return true;
1125           }
1126       }
1127
1128       gs.set_interrupt(0);
1129       return false;
1130     }
1131
1132   private:
1133     enum {
1134       STATE_START,
1135       STATE_CHECK_INDEX,
1136       STATE_CHECK_MCONTROL,
1137       STATE_WRITE_ADDRESS
1138     } state;
1139     hardware_breakpoint_t bp;
1140 };
1141
1142 class hardware_breakpoint_remove_op_t : public operation_t
1143 {
1144   public:
1145     hardware_breakpoint_remove_op_t(gdbserver_t& gdbserver,
1146         hardware_breakpoint_t bp) :
1147       operation_t(gdbserver), bp(bp) {};
1148
1149     bool perform_step(unsigned int step) {
1150       gs.dr_write32(0, addi(S0, ZERO, bp.index));
1151       gs.dr_write32(1, csrw(S0, CSR_TSELECT));
1152       gs.dr_write32(2, csrw(ZERO, CSR_TDATA0));
1153       gs.dr_write_jump(3);
1154       gs.set_interrupt(0);
1155       return true;
1156     }
1157
1158   private:
1159     hardware_breakpoint_t bp;
1160 };
1161
1162 ////////////////////////////// gdbserver itself
1163
1164 gdbserver_t::gdbserver_t(uint16_t port, sim_t *sim) :
1165   xlen(0),
1166   sim(sim),
1167   client_fd(0),
1168   recv_buf(64 * 1024), send_buf(64 * 1024)
1169 {
1170   socket_fd = socket(AF_INET, SOCK_STREAM, 0);
1171   if (socket_fd == -1) {
1172     fprintf(stderr, "failed to make socket: %s (%d)\n", strerror(errno), errno);
1173     abort();
1174   }
1175
1176   fcntl(socket_fd, F_SETFL, O_NONBLOCK);
1177   int reuseaddr = 1;
1178   if (setsockopt(socket_fd, SOL_SOCKET, SO_REUSEADDR, &reuseaddr,
1179         sizeof(int)) == -1) {
1180     fprintf(stderr, "failed setsockopt: %s (%d)\n", strerror(errno), errno);
1181     abort();
1182   }
1183
1184   struct sockaddr_in addr;
1185   memset(&addr, 0, sizeof(addr));
1186   addr.sin_family = AF_INET;
1187   addr.sin_addr.s_addr = INADDR_ANY;
1188   addr.sin_port = htons(port);
1189
1190   if (bind(socket_fd, (struct sockaddr *) &addr, sizeof(addr)) == -1) {
1191     fprintf(stderr, "failed to bind socket: %s (%d)\n", strerror(errno), errno);
1192     abort();
1193   }
1194
1195   if (listen(socket_fd, 1) == -1) {
1196     fprintf(stderr, "failed to listen on socket: %s (%d)\n", strerror(errno), errno);
1197     abort();
1198   }
1199 }
1200
1201 unsigned int gdbserver_t::find_access_size(reg_t address, int length)
1202 {
1203   reg_t composite = address | length;
1204   if ((composite & 0x7) == 0 && xlen >= 64)
1205     return 8;
1206   if ((composite & 0x3) == 0)
1207     return 4;
1208   return 1;
1209 }
1210
1211 reg_t gdbserver_t::translate(reg_t vaddr)
1212 {
1213   unsigned int vm = virtual_memory();
1214   unsigned int levels, ptidxbits, ptesize;
1215
1216   switch (vm) {
1217     case VM_MBARE:
1218       return vaddr;
1219
1220     case VM_SV32:
1221       levels = 2;
1222       ptidxbits = 10;
1223       ptesize = 4;
1224       break;
1225     case VM_SV39:
1226       levels = 3;
1227       ptidxbits = 9;
1228       ptesize = 8;
1229       break;
1230     case VM_SV48:
1231       levels = 4;
1232       ptidxbits = 9;
1233       ptesize = 8;
1234       break;
1235
1236     default:
1237       {
1238         char buf[100];
1239         sprintf(buf, "VM mode %d is not supported by gdbserver.cc.", vm);
1240         die(buf);
1241         return true;        // die doesn't return, but gcc doesn't know that.
1242       }
1243   }
1244
1245   // Handle page tables here. There's a bunch of duplicated code with
1246   // collect_translation_info_op_t. :-(
1247   reg_t base = sptbr << PGSHIFT;
1248   int ptshift = (levels - 1) * ptidxbits;
1249   for (unsigned int i = 0; i < levels; i++, ptshift -= ptidxbits) {
1250     reg_t idx = (vaddr >> (PGSHIFT + ptshift)) & ((1 << ptidxbits) - 1);
1251
1252     reg_t pte_addr = base + idx * ptesize;
1253     auto it = pte_cache.find(pte_addr);
1254     if (it == pte_cache.end()) {
1255       fprintf(stderr, "ERROR: gdbserver tried to translate 0x%lx without first "
1256           "collecting the relevant PTEs.\n", vaddr);
1257       die("gdbserver_t::translate()");
1258     }
1259
1260     reg_t pte = pte_cache[pte_addr];
1261     reg_t ppn = pte >> PTE_PPN_SHIFT;
1262
1263     if (PTE_TABLE(pte)) { // next level of page table
1264       base = ppn << PGSHIFT;
1265     } else {
1266       // We've collected all the data required for the translation.
1267       reg_t vpn = vaddr >> PGSHIFT;
1268       reg_t paddr = (ppn | (vpn & ((reg_t(1) << ptshift) - 1))) << PGSHIFT;
1269       paddr += vaddr & (PGSIZE-1);
1270       D(fprintf(stderr, "gdbserver translate 0x%lx -> 0x%lx\n", vaddr, paddr));
1271       return paddr;
1272     }
1273   }
1274
1275   fprintf(stderr, "ERROR: gdbserver tried to translate 0x%lx but the relevant "
1276       "PTEs are invalid.\n", vaddr);
1277   // TODO: Is it better to throw an exception here?
1278   return -1;
1279 }
1280
1281 unsigned int gdbserver_t::privilege_mode()
1282 {
1283   unsigned int mode = get_field(dcsr, DCSR_PRV);
1284   if (get_field(mstatus, MSTATUS_MPRV))
1285     mode = get_field(mstatus, MSTATUS_MPP);
1286   return mode;
1287 }
1288
1289 unsigned int gdbserver_t::virtual_memory()
1290 {
1291   unsigned int mode = privilege_mode();
1292   if (mode == PRV_M)
1293     return VM_MBARE;
1294   return get_field(mstatus, MSTATUS_VM);
1295 }
1296
1297 void gdbserver_t::dr_write32(unsigned int index, uint32_t value)
1298 {
1299   sim->debug_module.ram_write32(index, value);
1300 }
1301
1302 void gdbserver_t::dr_write64(unsigned int index, uint64_t value)
1303 {
1304   dr_write32(index, value);
1305   dr_write32(index+1, value >> 32);
1306 }
1307
1308 void gdbserver_t::dr_write(enum slot slot, uint64_t value)
1309 {
1310   switch (xlen) {
1311     case 32:
1312       dr_write32(slot_offset32[slot], value);
1313       break;
1314     case 64:
1315       dr_write64(slot_offset64[slot], value);
1316       break;
1317     case 128:
1318     default:
1319       abort();
1320   }
1321 }
1322
1323 void gdbserver_t::dr_write_jump(unsigned int index)
1324 {
1325   dr_write32(index, jal(0,
1326         (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*index))));
1327 }
1328
1329 void gdbserver_t::dr_write_store(unsigned int index, unsigned int reg, enum slot slot)
1330 {
1331   assert(slot != SLOT_INST0 || index > 2);
1332   assert(slot != SLOT_DATA0 || index < 4 || index > 6);
1333   assert(slot != SLOT_DATA1 || index < 5 || index > 10);
1334   assert(slot != SLOT_DATA_LAST || index < 6 || index > 14);
1335   switch (xlen) {
1336     case 32:
1337       return dr_write32(index,
1338           sw(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset32[slot]));
1339     case 64:
1340       return dr_write32(index,
1341           sd(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset64[slot]));
1342     case 128:
1343       return dr_write32(index,
1344           sq(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset128[slot]));
1345     default:
1346       fprintf(stderr, "xlen is %d!\n", xlen);
1347       abort();
1348   }
1349 }
1350
1351 void gdbserver_t::dr_write_load(unsigned int index, unsigned int reg, enum slot slot)
1352 {
1353   switch (xlen) {
1354     case 32:
1355       return dr_write32(index,
1356           lw(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset32[slot]));
1357     case 64:
1358       return dr_write32(index,
1359           ld(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset64[slot]));
1360     case 128:
1361       return dr_write32(index,
1362           lq(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset128[slot]));
1363     default:
1364       fprintf(stderr, "xlen is %d!\n", xlen);
1365       abort();
1366   }
1367 }
1368
1369 uint32_t gdbserver_t::dr_read32(unsigned int index)
1370 {
1371   uint32_t value = sim->debug_module.ram_read32(index);
1372   D(fprintf(stderr, "read32(%d) -> 0x%x\n", index, value));
1373   return value;
1374 }
1375
1376 uint64_t gdbserver_t::dr_read64(unsigned int index)
1377 {
1378   return ((uint64_t) dr_read32(index+1) << 32) | dr_read32(index);
1379 }
1380
1381 uint64_t gdbserver_t::dr_read(enum slot slot)
1382 {
1383   switch (xlen) {
1384     case 32:
1385       return dr_read32(slot_offset32[slot]);
1386     case 64:
1387       return dr_read64(slot_offset64[slot]);
1388     case 128:
1389       abort();
1390     default:
1391       abort();
1392   }
1393 }
1394
1395 void gdbserver_t::add_operation(operation_t* operation)
1396 {
1397   operation_queue.push(operation);
1398 }
1399
1400 void gdbserver_t::accept()
1401 {
1402   client_fd = ::accept(socket_fd, NULL, NULL);
1403   if (client_fd == -1) {
1404     if (errno == EAGAIN) {
1405       // No client waiting to connect right now.
1406     } else {
1407       fprintf(stderr, "failed to accept on socket: %s (%d)\n", strerror(errno),
1408           errno);
1409       abort();
1410     }
1411   } else {
1412     fcntl(client_fd, F_SETFL, O_NONBLOCK);
1413
1414     expect_ack = false;
1415     extended_mode = false;
1416
1417     // gdb wants the core to be halted when it attaches.
1418     add_operation(new halt_op_t(*this));
1419   }
1420 }
1421
1422 void gdbserver_t::read()
1423 {
1424   // Reading from a non-blocking socket still blocks if there is no data
1425   // available.
1426
1427   size_t count = recv_buf.contiguous_empty_size();
1428   assert(count > 0);
1429   ssize_t bytes = ::read(client_fd, recv_buf.contiguous_empty(), count);
1430   if (bytes == -1) {
1431     if (errno == EAGAIN) {
1432       // We'll try again the next call.
1433     } else {
1434       fprintf(stderr, "failed to read on socket: %s (%d)\n", strerror(errno), errno);
1435       abort();
1436     }
1437   } else if (bytes == 0) {
1438     // The remote disconnected.
1439     client_fd = 0;
1440     processor_t *p = sim->get_core(0);
1441     // TODO p->set_halted(false, HR_NONE);
1442     recv_buf.reset();
1443     send_buf.reset();
1444   } else {
1445     recv_buf.data_added(bytes);
1446   }
1447 }
1448
1449 void gdbserver_t::write()
1450 {
1451   if (send_buf.empty())
1452     return;
1453
1454   while (!send_buf.empty()) {
1455     unsigned int count = send_buf.contiguous_data_size();
1456     assert(count > 0);
1457     ssize_t bytes = ::write(client_fd, send_buf.contiguous_data(), count);
1458     if (bytes == -1) {
1459       fprintf(stderr, "failed to write to socket: %s (%d)\n", strerror(errno), errno);
1460       abort();
1461     } else if (bytes == 0) {
1462       // Client can't take any more data right now.
1463       break;
1464     } else {
1465       D(fprintf(stderr, "wrote %ld bytes: ", bytes));
1466       for (unsigned int i = 0; i < bytes; i++) {
1467         D(fprintf(stderr, "%c", send_buf[i]));
1468       }
1469       D(fprintf(stderr, "\n"));
1470       send_buf.consume(bytes);
1471     }
1472   }
1473 }
1474
1475 void print_packet(const std::vector<uint8_t> &packet)
1476 {
1477   for (uint8_t c : packet) {
1478     if (c >= ' ' and c <= '~')
1479       fprintf(stderr, "%c", c);
1480     else
1481       fprintf(stderr, "\\x%02x", c);
1482   }
1483   fprintf(stderr, "\n");
1484 }
1485
1486 uint8_t compute_checksum(const std::vector<uint8_t> &packet)
1487 {
1488   uint8_t checksum = 0;
1489   for (auto i = packet.begin() + 1; i != packet.end() - 3; i++ ) {
1490     checksum += *i;
1491   }
1492   return checksum;
1493 }
1494
1495 uint8_t character_hex_value(uint8_t character)
1496 {
1497   if (character >= '0' && character <= '9')
1498     return character - '0';
1499   if (character >= 'a' && character <= 'f')
1500     return 10 + character - 'a';
1501   if (character >= 'A' && character <= 'F')
1502     return 10 + character - 'A';
1503   return 0xff;
1504 }
1505
1506 uint8_t extract_checksum(const std::vector<uint8_t> &packet)
1507 {
1508   return character_hex_value(*(packet.end() - 1)) +
1509     16 * character_hex_value(*(packet.end() - 2));
1510 }
1511
1512 void gdbserver_t::process_requests()
1513 {
1514   // See https://sourceware.org/gdb/onlinedocs/gdb/Remote-Protocol.html
1515
1516   while (!recv_buf.empty()) {
1517     std::vector<uint8_t> packet;
1518     for (unsigned int i = 0; i < recv_buf.size(); i++) {
1519       uint8_t b = recv_buf[i];
1520
1521       if (packet.empty() && expect_ack && b == '+') {
1522         recv_buf.consume(1);
1523         break;
1524       }
1525
1526       if (packet.empty() && b == 3) {
1527         D(fprintf(stderr, "Received interrupt\n"));
1528         recv_buf.consume(1);
1529         handle_interrupt();
1530         break;
1531       }
1532
1533       if (b == '$') {
1534         // Start of new packet.
1535         if (!packet.empty()) {
1536           fprintf(stderr, "Received malformed %ld-byte packet from debug client: ",
1537               packet.size());
1538           print_packet(packet);
1539           recv_buf.consume(i);
1540           break;
1541         }
1542       }
1543
1544       packet.push_back(b);
1545
1546       // Packets consist of $<packet-data>#<checksum>
1547       // where <checksum> is
1548       if (packet.size() >= 4 &&
1549           packet[packet.size()-3] == '#') {
1550         handle_packet(packet);
1551         recv_buf.consume(i+1);
1552         break;
1553       }
1554     }
1555     // There's a partial packet in the buffer. Wait until we get more data to
1556     // process it.
1557     if (packet.size()) {
1558       break;
1559     }
1560   }
1561 }
1562
1563 void gdbserver_t::handle_halt_reason(const std::vector<uint8_t> &packet)
1564 {
1565   send_packet("S00");
1566 }
1567
1568 void gdbserver_t::handle_general_registers_read(const std::vector<uint8_t> &packet)
1569 {
1570   add_operation(new general_registers_read_op_t(*this));
1571 }
1572
1573 void gdbserver_t::set_interrupt(uint32_t hartid) {
1574   sim->debug_module.set_interrupt(hartid);
1575 }
1576
1577 // First byte is the most-significant one.
1578 // Eg. "08675309" becomes 0x08675309.
1579 uint64_t consume_hex_number(std::vector<uint8_t>::const_iterator &iter,
1580     std::vector<uint8_t>::const_iterator end)
1581 {
1582   uint64_t value = 0;
1583
1584   while (iter != end) {
1585     uint8_t c = *iter;
1586     uint64_t c_value = character_hex_value(c);
1587     if (c_value > 15)
1588       break;
1589     iter++;
1590     value <<= 4;
1591     value += c_value;
1592   }
1593   return value;
1594 }
1595
1596 // First byte is the least-significant one.
1597 // Eg. "08675309" becomes 0x09536708
1598 uint64_t consume_hex_number_le(std::vector<uint8_t>::const_iterator &iter,
1599     std::vector<uint8_t>::const_iterator end)
1600 {
1601   uint64_t value = 0;
1602   unsigned int shift = 4;
1603
1604   while (iter != end) {
1605     uint8_t c = *iter;
1606     uint64_t c_value = character_hex_value(c);
1607     if (c_value > 15)
1608       break;
1609     iter++;
1610     value |= c_value << shift;
1611     if ((shift % 8) == 0)
1612       shift += 12;
1613     else
1614       shift -= 4;
1615   }
1616   return value;
1617 }
1618
1619 void consume_string(std::string &str, std::vector<uint8_t>::const_iterator &iter,
1620     std::vector<uint8_t>::const_iterator end, uint8_t separator)
1621 {
1622   while (iter != end && *iter != separator) {
1623     str.append(1, (char) *iter);
1624     iter++;
1625   }
1626 }
1627
1628 void gdbserver_t::handle_register_read(const std::vector<uint8_t> &packet)
1629 {
1630   // p n
1631
1632   std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1633   unsigned int n = consume_hex_number(iter, packet.end());
1634   if (*iter != '#')
1635     return send_packet("E01");
1636
1637   add_operation(new register_read_op_t(*this, n));
1638 }
1639
1640 void gdbserver_t::handle_register_write(const std::vector<uint8_t> &packet)
1641 {
1642   // P n...=r...
1643
1644   std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1645   unsigned int n = consume_hex_number(iter, packet.end());
1646   if (*iter != '=')
1647     return send_packet("E05");
1648   iter++;
1649
1650   reg_t value = consume_hex_number_le(iter, packet.end());
1651   if (*iter != '#')
1652     return send_packet("E06");
1653
1654   processor_t *p = sim->get_core(0);
1655
1656   add_operation(new register_write_op_t(*this, n, value));
1657
1658   return send_packet("OK");
1659 }
1660
1661 void gdbserver_t::handle_memory_read(const std::vector<uint8_t> &packet)
1662 {
1663   // m addr,length
1664   std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1665   reg_t address = consume_hex_number(iter, packet.end());
1666   if (*iter != ',')
1667     return send_packet("E10");
1668   iter++;
1669   reg_t length = consume_hex_number(iter, packet.end());
1670   if (*iter != '#')
1671     return send_packet("E11");
1672
1673   add_operation(new collect_translation_info_op_t(*this, address, length));
1674   add_operation(new memory_read_op_t(*this, address, length));
1675 }
1676
1677 void gdbserver_t::handle_memory_binary_write(const std::vector<uint8_t> &packet)
1678 {
1679   // X addr,length:XX...
1680   std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1681   reg_t address = consume_hex_number(iter, packet.end());
1682   if (*iter != ',')
1683     return send_packet("E20");
1684   iter++;
1685   reg_t length = consume_hex_number(iter, packet.end());
1686   if (*iter != ':')
1687     return send_packet("E21");
1688   iter++;
1689
1690   if (length == 0) {
1691     return send_packet("OK");
1692   }
1693
1694   unsigned char *data = new unsigned char[length];
1695   for (unsigned int i = 0; i < length; i++) {
1696     if (iter == packet.end()) {
1697       return send_packet("E22");
1698     }
1699     uint8_t c = *iter;
1700     iter++;
1701     if (c == '}') {
1702       // The binary data representation uses 7d (ascii ‘}’) as an escape
1703       // character. Any escaped byte is transmitted as the escape character
1704       // followed by the original character XORed with 0x20. For example, the
1705       // byte 0x7d would be transmitted as the two bytes 0x7d 0x5d. The bytes
1706       // 0x23 (ascii ‘#’), 0x24 (ascii ‘$’), and 0x7d (ascii ‘}’) must always
1707       // be escaped.
1708       if (iter == packet.end()) {
1709         return send_packet("E23");
1710       }
1711       c = (*iter) ^ 0x20;
1712       iter++;
1713     }
1714     data[i] = c;
1715   }
1716   if (*iter != '#')
1717     return send_packet("E4b"); // EOVERFLOW
1718
1719   add_operation(new collect_translation_info_op_t(*this, address, length));
1720   add_operation(new memory_write_op_t(*this, address, length, data));
1721 }
1722
1723 void gdbserver_t::handle_continue(const std::vector<uint8_t> &packet)
1724 {
1725   // c [addr]
1726   processor_t *p = sim->get_core(0);
1727   if (packet[2] != '#') {
1728     std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1729     dpc = consume_hex_number(iter, packet.end());
1730     if (*iter != '#')
1731       return send_packet("E30");
1732   }
1733
1734   add_operation(new continue_op_t(*this, false));
1735 }
1736
1737 void gdbserver_t::handle_step(const std::vector<uint8_t> &packet)
1738 {
1739   // s [addr]
1740   if (packet[2] != '#') {
1741     std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1742     die("handle_step");
1743     //p->state.pc = consume_hex_number(iter, packet.end());
1744     if (*iter != '#')
1745       return send_packet("E40");
1746   }
1747
1748   add_operation(new continue_op_t(*this, true));
1749 }
1750
1751 void gdbserver_t::handle_kill(const std::vector<uint8_t> &packet)
1752 {
1753   // k
1754   // The exact effect of this packet is not specified.
1755   // Looks like OpenOCD disconnects?
1756   // TODO
1757 }
1758
1759 void gdbserver_t::handle_extended(const std::vector<uint8_t> &packet)
1760 {
1761   // Enable extended mode. In extended mode, the remote server is made
1762   // persistent. The ‘R’ packet is used to restart the program being debugged.
1763   send_packet("OK");
1764   extended_mode = true;
1765 }
1766
1767 void gdbserver_t::software_breakpoint_insert(reg_t vaddr, unsigned int size)
1768 {
1769   fence_i_required = true;
1770   add_operation(new collect_translation_info_op_t(*this, vaddr, size));
1771   unsigned char* inst = new unsigned char[4];
1772   if (size == 2) {
1773     inst[0] = C_EBREAK & 0xff;
1774     inst[1] = (C_EBREAK >> 8) & 0xff;
1775   } else {
1776     inst[0] = EBREAK & 0xff;
1777     inst[1] = (EBREAK >> 8) & 0xff;
1778     inst[2] = (EBREAK >> 16) & 0xff;
1779     inst[3] = (EBREAK >> 24) & 0xff;
1780   }
1781
1782   software_breakpoint_t bp = {
1783     .vaddr = vaddr,
1784     .size = size
1785   };
1786   software_breakpoints[vaddr] = bp;
1787   add_operation(new memory_read_op_t(*this, bp.vaddr, bp.size,
1788         software_breakpoints[bp.vaddr].instruction));
1789   add_operation(new memory_write_op_t(*this, bp.vaddr, bp.size, inst));
1790 }
1791
1792 void gdbserver_t::software_breakpoint_remove(reg_t vaddr, unsigned int size)
1793 {
1794   fence_i_required = true;
1795   add_operation(new collect_translation_info_op_t(*this, vaddr, size));
1796
1797   software_breakpoint_t found_bp = software_breakpoints[vaddr];
1798   unsigned char* instruction = new unsigned char[4];
1799   memcpy(instruction, found_bp.instruction, 4);
1800   add_operation(new memory_write_op_t(*this, found_bp.vaddr,
1801         found_bp.size, instruction));
1802   software_breakpoints.erase(vaddr);
1803 }
1804
1805 void gdbserver_t::hardware_breakpoint_insert(const hardware_breakpoint_t &bp)
1806 {
1807   add_operation(new hardware_breakpoint_insert_op_t(*this, bp));
1808 }
1809
1810 void gdbserver_t::hardware_breakpoint_remove(const hardware_breakpoint_t &bp)
1811 {
1812   hardware_breakpoint_t found = *hardware_breakpoints.find(bp);
1813   add_operation(new hardware_breakpoint_remove_op_t(*this, found));
1814 }
1815
1816 void gdbserver_t::handle_breakpoint(const std::vector<uint8_t> &packet)
1817 {
1818   // insert: Z type,addr,length
1819   // remove: z type,addr,length
1820
1821   // type: 0 - software breakpoint, 1 - hardware breakpoint, 2 - write
1822   // watchpoint, 3 - read watchpoint, 4 - access watchpoint; addr is address;
1823   // length is in bytes. For a software breakpoint, length specifies the size
1824   // of the instruction to be patched. For hardware breakpoints and watchpoints
1825   // length specifies the memory region to be monitored. To avoid potential
1826   // problems with duplicate packets, the operations should be implemented in
1827   // an idempotent way.
1828
1829   bool insert = (packet[1] == 'Z');
1830   std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1831   gdb_breakpoint_type_t type = static_cast<gdb_breakpoint_type_t>(
1832       consume_hex_number(iter, packet.end()));
1833   if (*iter != ',')
1834     return send_packet("E50");
1835   iter++;
1836   reg_t address = consume_hex_number(iter, packet.end());
1837   if (*iter != ',')
1838     return send_packet("E51");
1839   iter++;
1840   unsigned int size = consume_hex_number(iter, packet.end());
1841   // There may be more options after a ; here, but we don't support that.
1842   if (*iter != '#')
1843     return send_packet("E52");
1844
1845   switch (type) {
1846     case GB_SOFTWARE:
1847       if (size != 2 && size != 4) {
1848         return send_packet("E53");
1849       }
1850       if (insert) {
1851         software_breakpoint_insert(address, size);
1852       } else {
1853         software_breakpoint_remove(address, size);
1854       }
1855       break;
1856
1857     case GB_HARDWARE:
1858     case GB_WRITE:
1859     case GB_READ:
1860     case GB_ACCESS:
1861       {
1862         hardware_breakpoint_t bp = {
1863           .vaddr = address,
1864           .size = size
1865         };
1866         bp.load = (type == GB_READ || type == GB_ACCESS);
1867         bp.store = (type == GB_WRITE || type == GB_ACCESS);
1868         bp.execute = (type == GB_HARDWARE || type == GB_ACCESS);
1869         if (insert) {
1870           hardware_breakpoint_insert(bp);
1871           // Insert might fail if there's no space, so the insert operation will
1872           // send its own OK (or not).
1873           return;
1874         } else {
1875           hardware_breakpoint_remove(bp);
1876         }
1877       }
1878       break;
1879
1880     default:
1881       return send_packet("E56");
1882   }
1883
1884   return send_packet("OK");
1885 }
1886
1887 void gdbserver_t::handle_query(const std::vector<uint8_t> &packet)
1888 {
1889   std::string name;
1890   std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1891
1892   consume_string(name, iter, packet.end(), ':');
1893   if (iter != packet.end())
1894     iter++;
1895   if (name == "Supported") {
1896     start_packet();
1897     while (iter != packet.end()) {
1898       std::string feature;
1899       consume_string(feature, iter, packet.end(), ';');
1900       if (iter != packet.end())
1901         iter++;
1902       if (feature == "swbreak+") {
1903         send("swbreak+;");
1904       }
1905     }
1906     send("PacketSize=131072;");
1907     return end_packet();
1908   }
1909
1910   D(fprintf(stderr, "Unsupported query %s\n", name.c_str()));
1911   return send_packet("");
1912 }
1913
1914 void gdbserver_t::handle_packet(const std::vector<uint8_t> &packet)
1915 {
1916   if (compute_checksum(packet) != extract_checksum(packet)) {
1917     fprintf(stderr, "Received %ld-byte packet with invalid checksum\n", packet.size());
1918     fprintf(stderr, "Computed checksum: %x\n", compute_checksum(packet));
1919     print_packet(packet);
1920     send("-");
1921     return;
1922   }
1923
1924   D(fprintf(stderr, "Received %ld-byte packet from debug client: ", packet.size()));
1925   D(print_packet(packet));
1926   send("+");
1927
1928   switch (packet[1]) {
1929     case '!':
1930       return handle_extended(packet);
1931     case '?':
1932       return handle_halt_reason(packet);
1933     case 'g':
1934       return handle_general_registers_read(packet);
1935 //    case 'k':
1936 //      return handle_kill(packet);
1937     case 'm':
1938       return handle_memory_read(packet);
1939 //    case 'M':
1940 //      return handle_memory_write(packet);
1941     case 'X':
1942       return handle_memory_binary_write(packet);
1943     case 'p':
1944       return handle_register_read(packet);
1945     case 'P':
1946       return handle_register_write(packet);
1947     case 'c':
1948       return handle_continue(packet);
1949     case 's':
1950       return handle_step(packet);
1951     case 'z':
1952     case 'Z':
1953       return handle_breakpoint(packet);
1954     case 'q':
1955     case 'Q':
1956       return handle_query(packet);
1957   }
1958
1959   // Not supported.
1960   D(fprintf(stderr, "** Unsupported packet: "));
1961   D(print_packet(packet));
1962   send_packet("");
1963 }
1964
1965 void gdbserver_t::handle_interrupt()
1966 {
1967   processor_t *p = sim->get_core(0);
1968   add_operation(new halt_op_t(*this, true));
1969 }
1970
1971 void gdbserver_t::handle()
1972 {
1973   if (client_fd > 0) {
1974     processor_t *p = sim->get_core(0);
1975
1976     bool interrupt = sim->debug_module.get_interrupt(0);
1977
1978     if (!interrupt && !operation_queue.empty()) {
1979       operation_t *operation = operation_queue.front();
1980       if (operation->step()) {
1981         operation_queue.pop();
1982         delete operation;
1983       }
1984     }
1985
1986     bool halt_notification = sim->debug_module.get_halt_notification(0);
1987     if (halt_notification) {
1988       sim->debug_module.clear_halt_notification(0);
1989       add_operation(new halt_op_t(*this, true));
1990     }
1991
1992     this->read();
1993     this->write();
1994
1995   } else {
1996     this->accept();
1997   }
1998
1999   if (operation_queue.empty()) {
2000     this->process_requests();
2001   }
2002 }
2003
2004 void gdbserver_t::send(const char* msg)
2005 {
2006   unsigned int length = strlen(msg);
2007   for (const char *c = msg; *c; c++)
2008     running_checksum += *c;
2009   send_buf.append((const uint8_t *) msg, length);
2010 }
2011
2012 void gdbserver_t::send(uint64_t value)
2013 {
2014   char buffer[3];
2015   for (unsigned int i = 0; i < 8; i++) {
2016     sprintf(buffer, "%02x", (int) (value & 0xff));
2017     send(buffer);
2018     value >>= 8;
2019   }
2020 }
2021
2022 void gdbserver_t::send(uint32_t value)
2023 {
2024   char buffer[3];
2025   for (unsigned int i = 0; i < 4; i++) {
2026     sprintf(buffer, "%02x", (int) (value & 0xff));
2027     send(buffer);
2028     value >>= 8;
2029   }
2030 }
2031
2032 void gdbserver_t::send(uint8_t value)
2033 {
2034   char buffer[3];
2035   sprintf(buffer, "%02x", (int) value);
2036   send(buffer);
2037 }
2038
2039 void gdbserver_t::send_packet(const char* data)
2040 {
2041   start_packet();
2042   send(data);
2043   end_packet();
2044   expect_ack = true;
2045 }
2046
2047 void gdbserver_t::start_packet()
2048 {
2049   send("$");
2050   running_checksum = 0;
2051 }
2052
2053 void gdbserver_t::end_packet(const char* data)
2054 {
2055   if (data) {
2056     send(data);
2057   }
2058
2059   char checksum_string[4];
2060   sprintf(checksum_string, "#%02x", running_checksum);
2061   send(checksum_string);
2062   expect_ack = true;
2063 }