riscv/gdbserver.cc

   1 #include <arpa/inet.h>
   2 #include <errno.h>
   3 #include <fcntl.h>
   4 #include <stdlib.h>
   5 #include <string.h>
   6 #include <sys/socket.h>
   7 #include <sys/types.h>
   8 #include <unistd.h>
   9
  10 #include <algorithm>
  11 #include <cassert>
  12 #include <cinttypes>
  13 #include <cstdio>
  14 #include <vector>
  15
  16 #include "disasm.h"
  17 #include "sim.h"
  18 #include "gdbserver.h"
  19 #include "mmu.h"
  20
  21 #define C_EBREAK        0x9002
  22 #define EBREAK          0x00100073
  23
  24 //////////////////////////////////////// Utility Functions
  25
  26 #undef DEBUG
  27 #ifdef DEBUG
  28 #  define D(x) x
  29 #else
  30 #  define D(x)
  31 #endif // DEBUG
  32
  33 void die(const char* msg)
  34 {
  35   fprintf(stderr, "gdbserver code died: %s\n", msg);
  36   abort();
  37 }
  38
  39 // gdb's register list is defined in riscv_gdb_reg_names gdb/riscv-tdep.c in
  40 // its source tree. We must interpret the numbers the same here.
  41 enum {
  42   REG_XPR0 = 0,
  43   REG_XPR31 = 31,
  44   REG_PC = 32,
  45   REG_FPR0 = 33,
  46   REG_FPR31 = 64,
  47   REG_CSR0 = 65,
  48   REG_CSR4095 = 4160,
  49   REG_PRIV = 4161
  50 };
  51
  52 //////////////////////////////////////// Functions to generate RISC-V opcodes.
  53
  54 // TODO: Does this already exist somewhere?
  55
  56 #define ZERO    0
  57 // Using regnames.cc as source. The RVG Calling Convention of the 2.0 RISC-V
  58 // spec says it should be 2 and 3.
  59 #define S0      8
  60 #define S1      9
  61 static uint32_t bits(uint32_t value, unsigned int hi, unsigned int lo) {
  62   return (value >> lo) & ((1 << (hi+1-lo)) - 1);
  63 }
  64
  65 static uint32_t bit(uint32_t value, unsigned int b) {
  66   return (value >> b) & 1;
  67 }
  68
  69 static uint32_t jal(unsigned int rd, uint32_t imm) {
  70   return (bit(imm, 20) << 31) |
  71     (bits(imm, 10, 1) << 21) |
  72     (bit(imm, 11) << 20) |
  73     (bits(imm, 19, 12) << 12) |
  74     (rd << 7) |
  75     MATCH_JAL;
  76 }
  77
  78 static uint32_t csrsi(unsigned int csr, uint16_t imm) {
  79   return (csr << 20) |
  80     (bits(imm, 4, 0) << 15) |
  81     MATCH_CSRRSI;
  82 }
  83
  84 static uint32_t csrci(unsigned int csr, uint16_t imm) {
  85   return (csr << 20) |
  86     (bits(imm, 4, 0) << 15) |
  87     MATCH_CSRRCI;
  88 }
  89
  90 static uint32_t csrr(unsigned int rd, unsigned int csr) {
  91   return (csr << 20) | (rd << 7) | MATCH_CSRRS;
  92 }
  93
  94 static uint32_t csrw(unsigned int source, unsigned int csr) {
  95   return (csr << 20) | (source << 15) | MATCH_CSRRW;
  96 }
  97
  98 static uint32_t fence_i()
  99 {
 100   return MATCH_FENCE_I;
 101 }
 102
 103 static uint32_t sb(unsigned int src, unsigned int base, uint16_t offset)
 104 {
 105   return (bits(offset, 11, 5) << 25) |
 106     (src << 20) |
 107     (base << 15) |
 108     (bits(offset, 4, 0) << 7) |
 109     MATCH_SB;
 110 }
 111
 112 static uint32_t sh(unsigned int src, unsigned int base, uint16_t offset)
 113 {
 114   return (bits(offset, 11, 5) << 25) |
 115     (src << 20) |
 116     (base << 15) |
 117     (bits(offset, 4, 0) << 7) |
 118     MATCH_SH;
 119 }
 120
 121 static uint32_t sw(unsigned int src, unsigned int base, uint16_t offset)
 122 {
 123   return (bits(offset, 11, 5) << 25) |
 124     (src << 20) |
 125     (base << 15) |
 126     (bits(offset, 4, 0) << 7) |
 127     MATCH_SW;
 128 }
 129
 130 static uint32_t sd(unsigned int src, unsigned int base, uint16_t offset)
 131 {
 132   return (bits(offset, 11, 5) << 25) |
 133     (bits(src, 4, 0) << 20) |
 134     (base << 15) |
 135     (bits(offset, 4, 0) << 7) |
 136     MATCH_SD;
 137 }
 138
 139 static uint32_t sq(unsigned int src, unsigned int base, uint16_t offset)
 140 {
 141 #if 0
 142   return (bits(offset, 11, 5) << 25) |
 143     (bits(src, 4, 0) << 20) |
 144     (base << 15) |
 145     (bits(offset, 4, 0) << 7) |
 146     MATCH_SQ;
 147 #else
 148   abort();
 149 #endif
 150 }
 151
 152 static uint32_t lq(unsigned int rd, unsigned int base, uint16_t offset)
 153 {
 154 #if 0
 155   return (bits(offset, 11, 0) << 20) |
 156     (base << 15) |
 157     (bits(rd, 4, 0) << 7) |
 158     MATCH_LQ;
 159 #else
 160   abort();
 161 #endif
 162 }
 163
 164 static uint32_t ld(unsigned int rd, unsigned int base, uint16_t offset)
 165 {
 166   return (bits(offset, 11, 0) << 20) |
 167     (base << 15) |
 168     (bits(rd, 4, 0) << 7) |
 169     MATCH_LD;
 170 }
 171
 172 static uint32_t lw(unsigned int rd, unsigned int base, uint16_t offset)
 173 {
 174   return (bits(offset, 11, 0) << 20) |
 175     (base << 15) |
 176     (bits(rd, 4, 0) << 7) |
 177     MATCH_LW;
 178 }
 179
 180 static uint32_t lh(unsigned int rd, unsigned int base, uint16_t offset)
 181 {
 182   return (bits(offset, 11, 0) << 20) |
 183     (base << 15) |
 184     (bits(rd, 4, 0) << 7) |
 185     MATCH_LH;
 186 }
 187
 188 static uint32_t lb(unsigned int rd, unsigned int base, uint16_t offset)
 189 {
 190   return (bits(offset, 11, 0) << 20) |
 191     (base << 15) |
 192     (bits(rd, 4, 0) << 7) |
 193     MATCH_LB;
 194 }
 195
 196 static uint32_t fsw(unsigned int src, unsigned int base, uint16_t offset)
 197 {
 198   return (bits(offset, 11, 5) << 25) |
 199     (bits(src, 4, 0) << 20) |
 200     (base << 15) |
 201     (bits(offset, 4, 0) << 7) |
 202     MATCH_FSW;
 203 }
 204
 205 static uint32_t fsd(unsigned int src, unsigned int base, uint16_t offset)
 206 {
 207   return (bits(offset, 11, 5) << 25) |
 208     (bits(src, 4, 0) << 20) |
 209     (base << 15) |
 210     (bits(offset, 4, 0) << 7) |
 211     MATCH_FSD;
 212 }
 213
 214 static uint32_t flw(unsigned int src, unsigned int base, uint16_t offset)
 215 {
 216   return (bits(offset, 11, 5) << 25) |
 217     (bits(src, 4, 0) << 20) |
 218     (base << 15) |
 219     (bits(offset, 4, 0) << 7) |
 220     MATCH_FLW;
 221 }
 222
 223 static uint32_t fld(unsigned int src, unsigned int base, uint16_t offset)
 224 {
 225   return (bits(offset, 11, 5) << 25) |
 226     (bits(src, 4, 0) << 20) |
 227     (base << 15) |
 228     (bits(offset, 4, 0) << 7) |
 229     MATCH_FLD;
 230 }
 231
 232 static uint32_t addi(unsigned int dest, unsigned int src, uint16_t imm)
 233 {
 234   return (bits(imm, 11, 0) << 20) |
 235     (src << 15) |
 236     (dest << 7) |
 237     MATCH_ADDI;
 238 }
 239
 240 static uint32_t ori(unsigned int dest, unsigned int src, uint16_t imm)
 241 {
 242   return (bits(imm, 11, 0) << 20) |
 243     (src << 15) |
 244     (dest << 7) |
 245     MATCH_ORI;
 246 }
 247
 248 static uint32_t xori(unsigned int dest, unsigned int src, uint16_t imm)
 249 {
 250   return (bits(imm, 11, 0) << 20) |
 251     (src << 15) |
 252     (dest << 7) |
 253     MATCH_XORI;
 254 }
 255
 256 static uint32_t srli(unsigned int dest, unsigned int src, uint8_t shamt)
 257 {
 258   return (bits(shamt, 4, 0) << 20) |
 259     (src << 15) |
 260     (dest << 7) |
 261     MATCH_SRLI;
 262 }
 263
 264
 265 static uint32_t nop()
 266 {
 267   return addi(0, 0, 0);
 268 }
 269
 270 template <typename T>
 271 unsigned int circular_buffer_t<T>::size() const
 272 {
 273   if (end >= start)
 274     return end - start;
 275   else
 276     return end + capacity - start;
 277 }
 278
 279 template <typename T>
 280 void circular_buffer_t<T>::consume(unsigned int bytes)
 281 {
 282   start = (start + bytes) % capacity;
 283 }
 284
 285 template <typename T>
 286 unsigned int circular_buffer_t<T>::contiguous_empty_size() const
 287 {
 288   if (end >= start)
 289     if (start == 0)
 290       return capacity - end - 1;
 291     else
 292       return capacity - end;
 293   else
 294     return start - end - 1;
 295 }
 296
 297 template <typename T>
 298 unsigned int circular_buffer_t<T>::contiguous_data_size() const
 299 {
 300   if (end >= start)
 301     return end - start;
 302   else
 303     return capacity - start;
 304 }
 305
 306 template <typename T>
 307 void circular_buffer_t<T>::data_added(unsigned int bytes)
 308 {
 309   end += bytes;
 310   assert(end <= capacity);
 311   if (end == capacity)
 312     end = 0;
 313 }
 314
 315 template <typename T>
 316 void circular_buffer_t<T>::reset()
 317 {
 318   start = 0;
 319   end = 0;
 320 }
 321
 322 template <typename T>
 323 void circular_buffer_t<T>::append(const T *src, unsigned int count)
 324 {
 325   unsigned int copy = std::min(count, contiguous_empty_size());
 326   memcpy(contiguous_empty(), src, copy * sizeof(T));
 327   data_added(copy);
 328   count -= copy;
 329   if (count > 0) {
 330     assert(count < contiguous_empty_size());
 331     memcpy(contiguous_empty(), src, count * sizeof(T));
 332     data_added(count);
 333   }
 334 }
 335
 336 ////////////////////////////// Debug Operations
 337
 338 class halt_op_t : public operation_t
 339 {
 340   public:
 341     halt_op_t(gdbserver_t& gdbserver, bool send_status=false) :
 342       operation_t(gdbserver), send_status(send_status),
 343       state(ST_ENTER) {};
 344
 345     void write_dpc_program() {
 346       gs.dr_write32(0, csrsi(CSR_DCSR, DCSR_HALT));
 347       gs.dr_write32(1, csrr(S0, CSR_DPC));
 348       gs.dr_write_store(2, S0, SLOT_DATA0);
 349       gs.dr_write_jump(3);
 350       gs.set_interrupt(0);
 351     }
 352
 353     bool perform_step(unsigned int step) {
 354       switch (state) {
 355         gs.tselect_valid = false;
 356         case ST_ENTER:
 357           if (gs.xlen == 0) {
 358             gs.dr_write32(0, xori(S1, ZERO, -1));
 359             gs.dr_write32(1, srli(S1, S1, 31));
 360             // 0x00000001  0x00000001:ffffffff  0x00000001:ffffffff:ffffffff:ffffffff
 361             gs.dr_write32(2, sw(S1, ZERO, DEBUG_RAM_START));
 362             gs.dr_write32(3, srli(S1, S1, 31));
 363             // 0x00000000  0x00000000:00000003  0x00000000:00000003:ffffffff:ffffffff
 364             gs.dr_write32(4, sw(S1, ZERO, DEBUG_RAM_START + 4));
 365             gs.dr_write_jump(5);
 366             gs.set_interrupt(0);
 367             state = ST_XLEN;
 368
 369           } else {
 370             write_dpc_program();
 371             state = ST_DPC;
 372           }
 373           return false;
 374
 375         case ST_XLEN:
 376           {
 377             uint32_t word0 = gs.dr_read32(0);
 378             uint32_t word1 = gs.dr_read32(1);
 379
 380             if (word0 == 1 && word1 == 0) {
 381               gs.xlen = 32;
 382             } else if (word0 == 0xffffffff && word1 == 3) {
 383               gs.xlen = 64;
 384             } else if (word0 == 0xffffffff && word1 == 0xffffffff) {
 385               gs.xlen = 128;
 386             }
 387
 388             write_dpc_program();
 389             state = ST_DPC;
 390             return false;
 391           }
 392
 393         case ST_DPC:
 394           gs.dpc = gs.dr_read(SLOT_DATA0);
 395           gs.dr_write32(0, csrr(S0, CSR_MSTATUS));
 396           gs.dr_write_store(1, S0, SLOT_DATA0);
 397           gs.dr_write_jump(2);
 398           gs.set_interrupt(0);
 399           state = ST_MSTATUS;
 400           return false;
 401
 402         case ST_MSTATUS:
 403           gs.mstatus = gs.dr_read(SLOT_DATA0);
 404           gs.dr_write32(0, csrr(S0, CSR_DCSR));
 405           gs.dr_write32(1, sw(S0, 0, (uint16_t) DEBUG_RAM_START + 16));
 406           gs.dr_write_jump(2);
 407           gs.set_interrupt(0);
 408           state = ST_DCSR;
 409           return false;
 410
 411         case ST_DCSR:
 412           gs.dcsr = gs.dr_read32(4);
 413
 414           gs.sptbr_valid = false;
 415           gs.pte_cache.clear();
 416
 417           if (send_status) {
 418             switch (get_field(gs.dcsr, DCSR_CAUSE)) {
 419               case DCSR_CAUSE_NONE:
 420                 fprintf(stderr, "Internal error. Processor halted without reason.\n");
 421                 abort();
 422
 423               case DCSR_CAUSE_DEBUGINT:
 424                 gs.send_packet("S02");   // Pretend program received SIGINT.
 425                 break;
 426
 427               case DCSR_CAUSE_HWBP:
 428               case DCSR_CAUSE_STEP:
 429               case DCSR_CAUSE_HALT:
 430                 // There's no gdb code for this.
 431                 gs.send_packet("T05");
 432                 break;
 433               case DCSR_CAUSE_SWBP:
 434                 gs.send_packet("T05swbreak:;");
 435                 break;
 436             }
 437           }
 438           return true;
 439
 440         default:
 441           assert(0);
 442       }
 443     }
 444
 445   private:
 446     bool send_status;
 447     enum {
 448       ST_ENTER,
 449       ST_XLEN,
 450       ST_DPC,
 451       ST_MSTATUS,
 452       ST_DCSR
 453     } state;
 454 };
 455
 456 class continue_op_t : public operation_t
 457 {
 458   public:
 459     continue_op_t(gdbserver_t& gdbserver, bool single_step) :
 460       operation_t(gdbserver), single_step(single_step) {};
 461
 462     bool perform_step(unsigned int step) {
 463       D(fprintf(stderr, "continue step %d\n", step));
 464       switch (step) {
 465         case 0:
 466           gs.dr_write_load(0, S0, SLOT_DATA0);
 467           gs.dr_write32(1, csrw(S0, CSR_DPC));
 468           // TODO: Isn't there a fence.i in Debug ROM already?
 469           if (gs.fence_i_required) {
 470             gs.dr_write32(2, fence_i());
 471             gs.dr_write_jump(3);
 472             gs.fence_i_required = false;
 473           } else {
 474             gs.dr_write_jump(2);
 475           }
 476           gs.dr_write(SLOT_DATA0, gs.dpc);
 477           gs.set_interrupt(0);
 478           return false;
 479
 480         case 1:
 481           gs.dr_write_load(0, S0, SLOT_DATA0);
 482           gs.dr_write32(1, csrw(S0, CSR_MSTATUS));
 483           gs.dr_write_jump(2);
 484           gs.dr_write(SLOT_DATA0, gs.mstatus);
 485           gs.set_interrupt(0);
 486           return false;
 487
 488         case 2:
 489           gs.dr_write32(0, lw(S0, 0, (uint16_t) DEBUG_RAM_START+16));
 490           gs.dr_write32(1, csrw(S0, CSR_DCSR));
 491           gs.dr_write_jump(2);
 492
 493           reg_t dcsr = set_field(gs.dcsr, DCSR_HALT, 0);
 494           dcsr = set_field(dcsr, DCSR_STEP, single_step);
 495           // Software breakpoints should go here.
 496           dcsr = set_field(dcsr, DCSR_EBREAKM, 1);
 497           dcsr = set_field(dcsr, DCSR_EBREAKH, 1);
 498           dcsr = set_field(dcsr, DCSR_EBREAKS, 1);
 499           dcsr = set_field(dcsr, DCSR_EBREAKU, 1);
 500           gs.dr_write32(4, dcsr);
 501
 502           gs.set_interrupt(0);
 503           return true;
 504       }
 505       return false;
 506     }
 507
 508   private:
 509     bool single_step;
 510 };
 511
 512 class general_registers_read_op_t : public operation_t
 513 {
 514   // Register order that gdb expects is:
 515   //   "x0",  "x1",  "x2",  "x3",  "x4",  "x5",  "x6",  "x7",
 516   //   "x8",  "x9",  "x10", "x11", "x12", "x13", "x14", "x15",
 517   //   "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
 518   //   "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31",
 519
 520   // Each byte of register data is described by two hex digits. The bytes with
 521   // the register are transmitted in target byte order. The size of each
 522   // register and their position within the ‘g’ packet are determined by the
 523   // gdb internal gdbarch functions DEPRECATED_REGISTER_RAW_SIZE and
 524   // gdbarch_register_name.
 525
 526   public:
 527     general_registers_read_op_t(gdbserver_t& gdbserver) :
 528       operation_t(gdbserver) {};
 529
 530     bool perform_step(unsigned int step)
 531     {
 532       D(fprintf(stderr, "register_read step %d\n", step));
 533       if (step == 0) {
 534         gs.start_packet();
 535
 536         // x0 is always zero.
 537         if (gs.xlen == 32) {
 538           gs.send((uint32_t) 0);
 539         } else {
 540           gs.send((uint64_t) 0);
 541         }
 542
 543         gs.dr_write_store(0, 1, SLOT_DATA0);
 544         gs.dr_write_store(1, 2, SLOT_DATA1);
 545         gs.dr_write_jump(2);
 546         gs.set_interrupt(0);
 547         return false;
 548       }
 549
 550       if (gs.xlen == 32) {
 551         gs.send((uint32_t) gs.dr_read(SLOT_DATA0));
 552       } else {
 553         gs.send((uint64_t) gs.dr_read(SLOT_DATA0));
 554       }
 555       if (step >= 16) {
 556         gs.end_packet();
 557         return true;
 558       }
 559
 560       if (gs.xlen == 32) {
 561         gs.send((uint32_t) gs.dr_read(SLOT_DATA1));
 562       } else {
 563         gs.send((uint64_t) gs.dr_read(SLOT_DATA1));
 564       }
 565
 566       unsigned int current_reg = 2 * step + 1;
 567       unsigned int i = 0;
 568       if (current_reg == S1) {
 569         gs.dr_write_load(i++, S1, SLOT_DATA_LAST);
 570       }
 571       gs.dr_write_store(i++, current_reg, SLOT_DATA0);
 572       if (current_reg + 1 == S0) {
 573         gs.dr_write32(i++, csrr(S0, CSR_DSCRATCH));
 574       }
 575       if (step < 15) {
 576         gs.dr_write_store(i++, current_reg+1, SLOT_DATA1);
 577       }
 578       gs.dr_write_jump(i);
 579       gs.set_interrupt(0);
 580
 581       return false;
 582     }
 583 };
 584
 585 class register_read_op_t : public operation_t
 586 {
 587   public:
 588     register_read_op_t(gdbserver_t& gdbserver, unsigned int reg) :
 589       operation_t(gdbserver), reg(reg) {};
 590
 591     bool perform_step(unsigned int step)
 592     {
 593       switch (step) {
 594         case 0:
 595           if (reg >= REG_XPR0 && reg <= REG_XPR31) {
 596             die("handle_register_read");
 597             // send(p->state.XPR[reg - REG_XPR0]);
 598           } else if (reg == REG_PC) {
 599             gs.start_packet();
 600             if (gs.xlen == 32) {
 601               gs.send((uint32_t) gs.dpc);
 602             } else {
 603               gs.send(gs.dpc);
 604             }
 605             gs.end_packet();
 606             return true;
 607           } else if (reg >= REG_FPR0 && reg <= REG_FPR31) {
 608             // send(p->state.FPR[reg - REG_FPR0]);
 609             if (gs.xlen == 32) {
 610               gs.dr_write32(0, fsw(reg - REG_FPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
 611             } else {
 612               gs.dr_write32(0, fsd(reg - REG_FPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
 613             }
 614             gs.dr_write_jump(1);
 615           } else if (reg >= REG_CSR0 && reg <= REG_CSR4095) {
 616             gs.dr_write32(0, csrr(S0, reg - REG_CSR0));
 617             gs.dr_write_store(1, S0, SLOT_DATA0);
 618             gs.dr_write_jump(2);
 619             // If we hit an exception reading the CSR, we'll end up returning ~0 as
 620             // the register's value, which is what we want. (Right?)
 621             gs.dr_write(SLOT_DATA0, ~(uint64_t) 0);
 622           } else if (reg == REG_PRIV) {
 623             gs.start_packet();
 624             gs.send((uint8_t) get_field(gs.dcsr, DCSR_PRV));
 625             gs.end_packet();
 626             return true;
 627           } else {
 628             gs.send_packet("E02");
 629             return true;
 630           }
 631           gs.set_interrupt(0);
 632           return false;
 633
 634         case 1:
 635           gs.start_packet();
 636           if (gs.xlen == 32) {
 637             gs.send(gs.dr_read32(4));
 638           } else {
 639             gs.send(gs.dr_read(SLOT_DATA0));
 640           }
 641           gs.end_packet();
 642           return true;
 643       }
 644       return false;
 645     }
 646
 647   private:
 648     unsigned int reg;
 649 };
 650
 651 class register_write_op_t : public operation_t
 652 {
 653   public:
 654     register_write_op_t(gdbserver_t& gdbserver, unsigned int reg, reg_t value) :
 655       operation_t(gdbserver), reg(reg), value(value) {};
 656
 657     bool perform_step(unsigned int step)
 658     {
 659       gs.dr_write_load(0, S0, SLOT_DATA0);
 660       gs.dr_write(SLOT_DATA0, value);
 661       if (reg == S0) {
 662         gs.dr_write32(1, csrw(S0, CSR_DSCRATCH));
 663         gs.dr_write_jump(2);
 664       } else if (reg == S1) {
 665         gs.dr_write_store(1, S0, SLOT_DATA_LAST);
 666         gs.dr_write_jump(2);
 667       } else if (reg >= REG_XPR0 && reg <= REG_XPR31) {
 668         gs.dr_write32(1, addi(reg, S0, 0));
 669         gs.dr_write_jump(2);
 670       } else if (reg == REG_PC) {
 671         gs.dpc = value;
 672         return true;
 673       } else if (reg >= REG_FPR0 && reg <= REG_FPR31) {
 674         if (gs.xlen == 32) {
 675           gs.dr_write32(0, flw(reg - REG_FPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
 676         } else {
 677           gs.dr_write32(0, fld(reg - REG_FPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
 678         }
 679         gs.dr_write_jump(1);
 680       } else if (reg >= REG_CSR0 && reg <= REG_CSR4095) {
 681         gs.dr_write32(1, csrw(S0, reg - REG_CSR0));
 682         gs.dr_write_jump(2);
 683         if (reg == REG_CSR0 + CSR_SPTBR) {
 684           gs.sptbr = value;
 685           gs.sptbr_valid = true;
 686         }
 687       } else if (reg == REG_PRIV) {
 688         gs.dcsr = set_field(gs.dcsr, DCSR_PRV, value);
 689         return true;
 690       } else {
 691         gs.send_packet("E02");
 692         return true;
 693       }
 694       gs.set_interrupt(0);
 695       gs.send_packet("OK");
 696       return true;
 697     }
 698
 699   private:
 700     unsigned int reg;
 701     reg_t value;
 702 };
 703
 704 class memory_read_op_t : public operation_t
 705 {
 706   public:
 707     // Read length bytes from vaddr, storing the result into data.
 708     // If data is NULL, send the result straight to gdb.
 709     memory_read_op_t(gdbserver_t& gdbserver, reg_t vaddr, unsigned int length,
 710         unsigned char *data=NULL) :
 711       operation_t(gdbserver), vaddr(vaddr), length(length), data(data), index(0)
 712     {
 713       buf = new uint8_t[length];
 714     };
 715
 716     ~memory_read_op_t()
 717     {
 718       delete[] buf;
 719     }
 720
 721     bool perform_step(unsigned int step)
 722     {
 723       if (step == 0) {
 724         // address goes in S0
 725         paddr = gs.translate(vaddr);
 726         access_size = gs.find_access_size(paddr, length);
 727
 728         gs.dr_write_load(0, S0, SLOT_DATA0);
 729         switch (access_size) {
 730           case 1:
 731             gs.dr_write32(1, lb(S1, S0, 0));
 732             break;
 733           case 2:
 734             gs.dr_write32(1, lh(S1, S0, 0));
 735             break;
 736           case 4:
 737             gs.dr_write32(1, lw(S1, S0, 0));
 738             break;
 739           case 8:
 740             gs.dr_write32(1, ld(S1, S0, 0));
 741             break;
 742         }
 743         gs.dr_write_store(2, S1, SLOT_DATA1);
 744         gs.dr_write_jump(3);
 745         gs.dr_write(SLOT_DATA0, paddr);
 746         gs.set_interrupt(0);
 747
 748         return false;
 749       }
 750
 751       if (gs.dr_read32(DEBUG_RAM_SIZE / 4 - 1)) {
 752         // Note that OpenOCD doesn't report this error to gdb by default. They
 753         // think it can mess up stack tracing. So far I haven't seen any
 754         // problems.
 755         gs.send_packet("E99");
 756         return true;
 757       }
 758
 759       reg_t value = gs.dr_read(SLOT_DATA1);
 760       for (unsigned int i = 0; i < access_size; i++) {
 761         if (data) {
 762           *(data++) = value & 0xff;
 763           D(fprintf(stderr, "%02x", (unsigned int) (value & 0xff)));
 764         } else {
 765           buf[index++] = value & 0xff;
 766         }
 767         value >>= 8;
 768       }
 769       if (data) {
 770         D(fprintf(stderr, "\n"));
 771       }
 772       length -= access_size;
 773       paddr += access_size;
 774
 775       if (length == 0) {
 776         if (!data) {
 777           gs.start_packet();
 778           char buffer[3];
 779           for (unsigned int i = 0; i < index; i++) {
 780             sprintf(buffer, "%02x", (unsigned int) buf[i]);
 781             gs.send(buffer);
 782           }
 783           gs.end_packet();
 784         }
 785         return true;
 786       } else {
 787         gs.dr_write(SLOT_DATA0, paddr);
 788         gs.set_interrupt(0);
 789         return false;
 790       }
 791     }
 792
 793   private:
 794     reg_t vaddr;
 795     unsigned int length;
 796     unsigned char* data;
 797     reg_t paddr;
 798     unsigned int access_size;
 799     unsigned int index;
 800     uint8_t *buf;
 801 };
 802
 803 class memory_write_op_t : public operation_t
 804 {
 805   public:
 806     memory_write_op_t(gdbserver_t& gdbserver, reg_t vaddr, unsigned int length,
 807         const unsigned char *data) :
 808       operation_t(gdbserver), vaddr(vaddr), offset(0), length(length), data(data) {};
 809
 810     ~memory_write_op_t() {
 811       delete[] data;
 812     }
 813
 814     bool perform_step(unsigned int step)
 815     {
 816       reg_t paddr = gs.translate(vaddr);
 817
 818       unsigned int data_offset;
 819       switch (gs.xlen) {
 820         case 32:
 821           data_offset = slot_offset32[SLOT_DATA1];
 822           break;
 823         case 64:
 824           data_offset = slot_offset64[SLOT_DATA1];
 825           break;
 826         case 128:
 827           data_offset = slot_offset128[SLOT_DATA1];
 828           break;
 829         default:
 830           abort();
 831       }
 832
 833       if (step == 0) {
 834         access_size = gs.find_access_size(paddr, length);
 835
 836         D(fprintf(stderr, "write to 0x%lx -> 0x%lx (access=%d): ", vaddr, paddr,
 837             access_size));
 838         for (unsigned int i = 0; i < length; i++) {
 839           D(fprintf(stderr, "%02x", data[i]));
 840         }
 841         D(fprintf(stderr, "\n"));
 842
 843         // address goes in S0
 844         gs.dr_write_load(0, S0, SLOT_DATA0);
 845         switch (access_size) {
 846           case 1:
 847             gs.dr_write32(1, lb(S1, 0, (uint16_t) DEBUG_RAM_START + 4*data_offset));
 848             gs.dr_write32(2, sb(S1, S0, 0));
 849             gs.dr_write32(data_offset, data[0]);
 850             break;
 851           case 2:
 852             gs.dr_write32(1, lh(S1, 0, (uint16_t) DEBUG_RAM_START + 4*data_offset));
 853             gs.dr_write32(2, sh(S1, S0, 0));
 854             gs.dr_write32(data_offset, data[0] | (data[1] << 8));
 855             break;
 856           case 4:
 857             gs.dr_write32(1, lw(S1, 0, (uint16_t) DEBUG_RAM_START + 4*data_offset));
 858             gs.dr_write32(2, sw(S1, S0, 0));
 859             gs.dr_write32(data_offset, data[0] | (data[1] << 8) |
 860                 (data[2] << 16) | (data[3] << 24));
 861             break;
 862           case 8:
 863             gs.dr_write32(1, ld(S1, 0, (uint16_t) DEBUG_RAM_START + 4*data_offset));
 864             gs.dr_write32(2, sd(S1, S0, 0));
 865             gs.dr_write32(data_offset, data[0] | (data[1] << 8) |
 866                 (data[2] << 16) | (data[3] << 24));
 867             gs.dr_write32(data_offset+1, data[4] | (data[5] << 8) |
 868                 (data[6] << 16) | (data[7] << 24));
 869             break;
 870           default:
 871             fprintf(stderr, "gdbserver error: write %d bytes to 0x%016" PRIx64
 872                     " -> 0x%016" PRIx64 "; access_size=%d\n",
 873                     length, vaddr, paddr, access_size);
 874             gs.send_packet("E12");
 875             return true;
 876         }
 877         gs.dr_write_jump(3);
 878         gs.dr_write(SLOT_DATA0, paddr);
 879         gs.set_interrupt(0);
 880
 881         return false;
 882       }
 883
 884       if (gs.dr_read32(DEBUG_RAM_SIZE / 4 - 1)) {
 885         fprintf(stderr, "Exception happened while writing to 0x%016" PRIx64
 886                 " -> 0x%016" PRIx64 "\n", vaddr, paddr);
 887       }
 888
 889       offset += access_size;
 890       if (offset >= length) {
 891         gs.send_packet("OK");
 892         return true;
 893       } else {
 894         const unsigned char *d = data + offset;
 895         switch (access_size) {
 896           case 1:
 897             gs.dr_write32(data_offset, d[0]);
 898             break;
 899           case 2:
 900             gs.dr_write32(data_offset, d[0] | (d[1] << 8));
 901             break;
 902           case 4:
 903             gs.dr_write32(data_offset, d[0] | (d[1] << 8) |
 904                 (d[2] << 16) | (d[3] << 24));
 905             break;
 906           case 8:
 907             gs.dr_write32(data_offset, d[0] | (d[1] << 8) |
 908                 (d[2] << 16) | (d[3] << 24));
 909             gs.dr_write32(data_offset+1, d[4] | (d[5] << 8) |
 910                 (d[6] << 16) | (d[7] << 24));
 911             break;
 912           default:
 913             gs.send_packet("E13");
 914             return true;
 915         }
 916         gs.dr_write(SLOT_DATA0, paddr + offset);
 917         gs.set_interrupt(0);
 918         return false;
 919       }
 920     }
 921
 922   private:
 923     reg_t vaddr;
 924     unsigned int offset;
 925     unsigned int length;
 926     unsigned int access_size;
 927     const unsigned char *data;
 928 };
 929
 930 class collect_translation_info_op_t : public operation_t
 931 {
 932   public:
 933     // Read sufficient information from the target into gdbserver structures so
 934     // that it's possible to translate vaddr, vaddr+length, and all addresses
 935     // in between to physical addresses.
 936     collect_translation_info_op_t(gdbserver_t& gdbserver, reg_t vaddr, size_t length) :
 937       operation_t(gdbserver), state(STATE_START), vaddr(vaddr), length(length) {};
 938
 939     bool perform_step(unsigned int step)
 940     {
 941       unsigned int vm = gs.virtual_memory();
 942
 943       if (step == 0) {
 944         switch (vm) {
 945           case VM_MBARE:
 946             // Nothing to be done.
 947             return true;
 948
 949           case VM_SV32:
 950             levels = 2;
 951             ptidxbits = 10;
 952             ptesize = 4;
 953             break;
 954           case VM_SV39:
 955             levels = 3;
 956             ptidxbits = 9;
 957             ptesize = 8;
 958             break;
 959           case VM_SV48:
 960             levels = 4;
 961             ptidxbits = 9;
 962             ptesize = 8;
 963             break;
 964
 965           default:
 966             {
 967               char buf[100];
 968               sprintf(buf, "VM mode %d is not supported by gdbserver.cc.", vm);
 969               die(buf);
 970               return true;        // die doesn't return, but gcc doesn't know that.
 971             }
 972         }
 973       }
 974
 975       // Perform any reads from the just-completed action.
 976       switch (state) {
 977         case STATE_START:
 978           break;
 979         case STATE_READ_SPTBR:
 980           gs.sptbr = gs.dr_read(SLOT_DATA0);
 981           gs.sptbr_valid = true;
 982           break;
 983         case STATE_READ_PTE:
 984           if (ptesize == 4) {
 985               gs.pte_cache[pte_addr] = gs.dr_read32(4);
 986           } else {
 987               gs.pte_cache[pte_addr] = ((uint64_t) gs.dr_read32(5) << 32) |
 988                   gs.dr_read32(4);
 989           }
 990           D(fprintf(stderr, "pte_cache[0x%lx] = 0x%lx\n", pte_addr, gs.pte_cache[pte_addr]));
 991           break;
 992       }
 993
 994       // Set up the next action.
 995       // We only get here for VM_SV32/39/38.
 996
 997       if (!gs.sptbr_valid) {
 998         state = STATE_READ_SPTBR;
 999         gs.dr_write32(0, csrr(S0, CSR_SPTBR));
1000         gs.dr_write_store(1, S0, SLOT_DATA0);
1001         gs.dr_write_jump(2);
1002         gs.set_interrupt(0);
1003         return false;
1004       }
1005
1006       reg_t base = gs.sptbr << PGSHIFT;
1007       int ptshift = (levels - 1) * ptidxbits;
1008       for (unsigned int i = 0; i < levels; i++, ptshift -= ptidxbits) {
1009         reg_t idx = (vaddr >> (PGSHIFT + ptshift)) & ((1 << ptidxbits) - 1);
1010
1011         pte_addr = base + idx * ptesize;
1012         auto it = gs.pte_cache.find(pte_addr);
1013         if (it == gs.pte_cache.end()) {
1014           state = STATE_READ_PTE;
1015           if (ptesize == 4) {
1016             gs.dr_write32(0, lw(S0, 0, (uint16_t) DEBUG_RAM_START + 16));
1017             gs.dr_write32(1, lw(S1, S0, 0));
1018             gs.dr_write32(2, sw(S1, 0, (uint16_t) DEBUG_RAM_START + 16));
1019           } else {
1020             assert(gs.xlen >= 64);
1021             gs.dr_write32(0, ld(S0, 0, (uint16_t) DEBUG_RAM_START + 16));
1022             gs.dr_write32(1, ld(S1, S0, 0));
1023             gs.dr_write32(2, sd(S1, 0, (uint16_t) DEBUG_RAM_START + 16));
1024           }
1025           gs.dr_write32(3, jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*3))));
1026           gs.dr_write32(4, pte_addr);
1027           gs.dr_write32(5, pte_addr >> 32);
1028           gs.set_interrupt(0);
1029           return false;
1030         }
1031
1032         reg_t pte = gs.pte_cache[pte_addr];
1033         reg_t ppn = pte >> PTE_PPN_SHIFT;
1034
1035         if (PTE_TABLE(pte)) { // next level of page table
1036           base = ppn << PGSHIFT;
1037         } else {
1038           // We've collected all the data required for the translation.
1039           return true;
1040         }
1041       }
1042       fprintf(stderr,
1043           "ERROR: gdbserver couldn't find appropriate PTEs to translate 0x%016" PRIx64 "\n",
1044           vaddr);
1045       return true;
1046     }
1047
1048   private:
1049     enum {
1050       STATE_START,
1051       STATE_READ_SPTBR,
1052       STATE_READ_PTE
1053     } state;
1054     reg_t vaddr;
1055     size_t length;
1056     unsigned int levels;
1057     unsigned int ptidxbits;
1058     unsigned int ptesize;
1059     reg_t pte_addr;
1060 };
1061
1062 class hardware_breakpoint_insert_op_t : public operation_t
1063 {
1064   public:
1065     hardware_breakpoint_insert_op_t(gdbserver_t& gdbserver,
1066         hardware_breakpoint_t bp) :
1067       operation_t(gdbserver), state(STATE_START), bp(bp) {};
1068
1069     void write_new_index_program()
1070     {
1071       gs.dr_write_load(0, S0, SLOT_DATA1);
1072       gs.dr_write32(1, csrw(S0, CSR_TSELECT));
1073       gs.dr_write32(2, csrr(S0, CSR_TSELECT));
1074       gs.dr_write_store(3, S0, SLOT_DATA1);
1075       gs.dr_write_jump(4);
1076       gs.dr_write(SLOT_DATA1, bp.index);
1077     }
1078
1079     bool perform_step(unsigned int step)
1080     {
1081       switch (state) {
1082         case STATE_START:
1083           bp.index = 0;
1084           write_new_index_program();
1085           state = STATE_CHECK_INDEX;
1086           break;
1087
1088         case STATE_CHECK_INDEX:
1089           if (gs.dr_read(SLOT_DATA1) != bp.index) {
1090             // We've exhausted breakpoints without finding an appropriate one.
1091             gs.send_packet("E58");
1092             return true;
1093           }
1094
1095           gs.dr_write32(0, csrr(S0, CSR_TDATA1));
1096           gs.dr_write_store(1, S0, SLOT_DATA0);
1097           gs.dr_write_jump(2);
1098           state = STATE_CHECK_MCONTROL;
1099           break;
1100
1101         case STATE_CHECK_MCONTROL:
1102           {
1103             reg_t mcontrol = gs.dr_read(SLOT_DATA0);
1104             unsigned int type = mcontrol >> (gs.xlen - 4);
1105             if (type == 0) {
1106               // We've exhausted breakpoints without finding an appropriate one.
1107               gs.send_packet("E58");
1108               return true;
1109             }
1110
1111             if (type == 2 &&
1112                 !get_field(mcontrol, MCONTROL_EXECUTE) &&
1113                 !get_field(mcontrol, MCONTROL_LOAD) &&
1114                 !get_field(mcontrol, MCONTROL_STORE)) {
1115               // Found an unused trigger.
1116               gs.dr_write_load(0, S0, SLOT_DATA1);
1117               gs.dr_write32(1, csrw(S0, CSR_TDATA1));
1118               gs.dr_write_jump(2);
1119               mcontrol = set_field(0, MCONTROL_ACTION, MCONTROL_ACTION_DEBUG_MODE);
1120               mcontrol = set_field(mcontrol, MCONTROL_DMODE(gs.xlen), 1);
1121               mcontrol = set_field(mcontrol, MCONTROL_MATCH, MCONTROL_MATCH_EQUAL);
1122               mcontrol = set_field(mcontrol, MCONTROL_M, 1);
1123               mcontrol = set_field(mcontrol, MCONTROL_H, 1);
1124               mcontrol = set_field(mcontrol, MCONTROL_S, 1);
1125               mcontrol = set_field(mcontrol, MCONTROL_U, 1);
1126               mcontrol = set_field(mcontrol, MCONTROL_EXECUTE, bp.execute);
1127               mcontrol = set_field(mcontrol, MCONTROL_LOAD, bp.load);
1128               mcontrol = set_field(mcontrol, MCONTROL_STORE, bp.store);
1129               // For store triggers it's nicer to fire just before the
1130               // instruction than just after. However, gdb doesn't clear the
1131               // breakpoints and step before resuming from a store trigger.
1132               // That means that without extra code, you'll keep hitting the
1133               // same watchpoint over and over again. That's not useful at all.
1134               // Instead of fixing this the right way, just set timing=1 for
1135               // those triggers.
1136               if (bp.load || bp.store)
1137                 mcontrol = set_field(mcontrol, MCONTROL_TIMING, 1);
1138
1139               gs.dr_write(SLOT_DATA1, mcontrol);
1140               state = STATE_WRITE_ADDRESS;
1141             } else {
1142               bp.index++;
1143               write_new_index_program();
1144               state = STATE_CHECK_INDEX;
1145             }
1146           }
1147           break;
1148
1149         case STATE_WRITE_ADDRESS:
1150           {
1151             gs.dr_write_load(0, S0, SLOT_DATA1);
1152             gs.dr_write32(1, csrw(S0, CSR_TDATA2));
1153             gs.dr_write_jump(2);
1154             gs.dr_write(SLOT_DATA1, bp.vaddr);
1155             gs.set_interrupt(0);
1156             gs.send_packet("OK");
1157
1158             gs.hardware_breakpoints.insert(bp);
1159
1160             return true;
1161           }
1162       }
1163
1164       gs.set_interrupt(0);
1165       return false;
1166     }
1167
1168   private:
1169     enum {
1170       STATE_START,
1171       STATE_CHECK_INDEX,
1172       STATE_CHECK_MCONTROL,
1173       STATE_WRITE_ADDRESS
1174     } state;
1175     hardware_breakpoint_t bp;
1176 };
1177
1178 class maybe_save_tselect_op_t : public operation_t
1179 {
1180   public:
1181     maybe_save_tselect_op_t(gdbserver_t& gdbserver) : operation_t(gdbserver) {};
1182     bool perform_step(unsigned int step) {
1183       if (gs.tselect_valid)
1184         return true;
1185
1186       switch (step) {
1187         case 0:
1188           gs.dr_write32(0, csrr(S0, CSR_TDATA1));
1189           gs.dr_write_store(1, S0, SLOT_DATA0);
1190           gs.dr_write_jump(2);
1191           gs.set_interrupt(0);
1192           return false;
1193         case 1:
1194           gs.tselect = gs.dr_read(SLOT_DATA0);
1195           gs.tselect_valid = true;
1196           break;
1197       }
1198       return true;
1199     }
1200 };
1201
1202 class maybe_restore_tselect_op_t : public operation_t
1203 {
1204   public:
1205     maybe_restore_tselect_op_t(gdbserver_t& gdbserver) : operation_t(gdbserver) {};
1206     bool perform_step(unsigned int step) {
1207       if (gs.tselect_valid) {
1208         gs.dr_write_load(0, S0, SLOT_DATA1);
1209         gs.dr_write32(1, csrw(S0, CSR_TSELECT));
1210         gs.dr_write_jump(2);
1211         gs.dr_write(SLOT_DATA1, gs.tselect);
1212       }
1213       return true;
1214     }
1215 };
1216
1217 class hardware_breakpoint_remove_op_t : public operation_t
1218 {
1219   public:
1220     hardware_breakpoint_remove_op_t(gdbserver_t& gdbserver,
1221         hardware_breakpoint_t bp) :
1222       operation_t(gdbserver), bp(bp) {};
1223
1224     bool perform_step(unsigned int step) {
1225       gs.dr_write32(0, addi(S0, ZERO, bp.index));
1226       gs.dr_write32(1, csrw(S0, CSR_TSELECT));
1227       gs.dr_write32(2, csrw(ZERO, CSR_TDATA1));
1228       gs.dr_write_jump(3);
1229       gs.set_interrupt(0);
1230       return true;
1231     }
1232
1233   private:
1234     hardware_breakpoint_t bp;
1235 };
1236
1237 ////////////////////////////// gdbserver itself
1238
1239 gdbserver_t::gdbserver_t(uint16_t port, sim_t *sim) :
1240   xlen(0),
1241   sim(sim),
1242   client_fd(0),
1243   recv_buf(64 * 1024), send_buf(64 * 1024)
1244 {
1245   socket_fd = socket(AF_INET, SOCK_STREAM, 0);
1246   if (socket_fd == -1) {
1247     fprintf(stderr, "failed to make socket: %s (%d)\n", strerror(errno), errno);
1248     abort();
1249   }
1250
1251   fcntl(socket_fd, F_SETFL, O_NONBLOCK);
1252   int reuseaddr = 1;
1253   if (setsockopt(socket_fd, SOL_SOCKET, SO_REUSEADDR, &reuseaddr,
1254         sizeof(int)) == -1) {
1255     fprintf(stderr, "failed setsockopt: %s (%d)\n", strerror(errno), errno);
1256     abort();
1257   }
1258
1259   struct sockaddr_in addr;
1260   memset(&addr, 0, sizeof(addr));
1261   addr.sin_family = AF_INET;
1262   addr.sin_addr.s_addr = INADDR_ANY;
1263   addr.sin_port = htons(port);
1264
1265   if (bind(socket_fd, (struct sockaddr *) &addr, sizeof(addr)) == -1) {
1266     fprintf(stderr, "failed to bind socket: %s (%d)\n", strerror(errno), errno);
1267     abort();
1268   }
1269
1270   if (listen(socket_fd, 1) == -1) {
1271     fprintf(stderr, "failed to listen on socket: %s (%d)\n", strerror(errno), errno);
1272     abort();
1273   }
1274 }
1275
1276 unsigned int gdbserver_t::find_access_size(reg_t address, int length)
1277 {
1278   reg_t composite = address | length;
1279   if ((composite & 0x7) == 0 && xlen >= 64)
1280     return 8;
1281   if ((composite & 0x3) == 0)
1282     return 4;
1283   return 1;
1284 }
1285
1286 reg_t gdbserver_t::translate(reg_t vaddr)
1287 {
1288   unsigned int vm = virtual_memory();
1289   unsigned int levels, ptidxbits, ptesize;
1290
1291   switch (vm) {
1292     case VM_MBARE:
1293       return vaddr;
1294
1295     case VM_SV32:
1296       levels = 2;
1297       ptidxbits = 10;
1298       ptesize = 4;
1299       break;
1300     case VM_SV39:
1301       levels = 3;
1302       ptidxbits = 9;
1303       ptesize = 8;
1304       break;
1305     case VM_SV48:
1306       levels = 4;
1307       ptidxbits = 9;
1308       ptesize = 8;
1309       break;
1310
1311     default:
1312       {
1313         char buf[100];
1314         sprintf(buf, "VM mode %d is not supported by gdbserver.cc.", vm);
1315         die(buf);
1316         return true;        // die doesn't return, but gcc doesn't know that.
1317       }
1318   }
1319
1320   // Handle page tables here. There's a bunch of duplicated code with
1321   // collect_translation_info_op_t. :-(
1322   reg_t base = sptbr << PGSHIFT;
1323   int ptshift = (levels - 1) * ptidxbits;
1324   for (unsigned int i = 0; i < levels; i++, ptshift -= ptidxbits) {
1325     reg_t idx = (vaddr >> (PGSHIFT + ptshift)) & ((1 << ptidxbits) - 1);
1326
1327     reg_t pte_addr = base + idx * ptesize;
1328     auto it = pte_cache.find(pte_addr);
1329     if (it == pte_cache.end()) {
1330       fprintf(stderr, "ERROR: gdbserver tried to translate 0x%016" PRIx64
1331           " without first collecting the relevant PTEs.\n", vaddr);
1332       die("gdbserver_t::translate()");
1333     }
1334
1335     reg_t pte = pte_cache[pte_addr];
1336     reg_t ppn = pte >> PTE_PPN_SHIFT;
1337
1338     if (PTE_TABLE(pte)) { // next level of page table
1339       base = ppn << PGSHIFT;
1340     } else {
1341       // We've collected all the data required for the translation.
1342       reg_t vpn = vaddr >> PGSHIFT;
1343       reg_t paddr = (ppn | (vpn & ((reg_t(1) << ptshift) - 1))) << PGSHIFT;
1344       paddr += vaddr & (PGSIZE-1);
1345       D(fprintf(stderr, "gdbserver translate 0x%lx -> 0x%lx\n", vaddr, paddr));
1346       return paddr;
1347     }
1348   }
1349
1350   fprintf(stderr, "ERROR: gdbserver tried to translate 0x%016" PRIx64
1351           " but the relevant PTEs are invalid.\n", vaddr);
1352   // TODO: Is it better to throw an exception here?
1353   return -1;
1354 }
1355
1356 unsigned int gdbserver_t::privilege_mode()
1357 {
1358   unsigned int mode = get_field(dcsr, DCSR_PRV);
1359   if (get_field(mstatus, MSTATUS_MPRV))
1360     mode = get_field(mstatus, MSTATUS_MPP);
1361   return mode;
1362 }
1363
1364 unsigned int gdbserver_t::virtual_memory()
1365 {
1366   unsigned int mode = privilege_mode();
1367   if (mode == PRV_M)
1368     return VM_MBARE;
1369   return get_field(mstatus, MSTATUS_VM);
1370 }
1371
1372 void gdbserver_t::dr_write32(unsigned int index, uint32_t value)
1373 {
1374   sim->debug_module.ram_write32(index, value);
1375 }
1376
1377 void gdbserver_t::dr_write64(unsigned int index, uint64_t value)
1378 {
1379   dr_write32(index, value);
1380   dr_write32(index+1, value >> 32);
1381 }
1382
1383 void gdbserver_t::dr_write(enum slot slot, uint64_t value)
1384 {
1385   switch (xlen) {
1386     case 32:
1387       dr_write32(slot_offset32[slot], value);
1388       break;
1389     case 64:
1390       dr_write64(slot_offset64[slot], value);
1391       break;
1392     case 128:
1393     default:
1394       abort();
1395   }
1396 }
1397
1398 void gdbserver_t::dr_write_jump(unsigned int index)
1399 {
1400   dr_write32(index, jal(0,
1401         (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*index))));
1402 }
1403
1404 void gdbserver_t::dr_write_store(unsigned int index, unsigned int reg, enum slot slot)
1405 {
1406   assert(slot != SLOT_INST0 || index > 2);
1407   assert(slot != SLOT_DATA0 || index < 4 || index > 6);
1408   assert(slot != SLOT_DATA1 || index < 5 || index > 10);
1409   assert(slot != SLOT_DATA_LAST || index < 6 || index > 14);
1410   switch (xlen) {
1411     case 32:
1412       return dr_write32(index,
1413           sw(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset32[slot]));
1414     case 64:
1415       return dr_write32(index,
1416           sd(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset64[slot]));
1417     case 128:
1418       return dr_write32(index,
1419           sq(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset128[slot]));
1420     default:
1421       fprintf(stderr, "xlen is %d!\n", xlen);
1422       abort();
1423   }
1424 }
1425
1426 void gdbserver_t::dr_write_load(unsigned int index, unsigned int reg, enum slot slot)
1427 {
1428   switch (xlen) {
1429     case 32:
1430       return dr_write32(index,
1431           lw(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset32[slot]));
1432     case 64:
1433       return dr_write32(index,
1434           ld(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset64[slot]));
1435     case 128:
1436       return dr_write32(index,
1437           lq(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset128[slot]));
1438     default:
1439       fprintf(stderr, "xlen is %d!\n", xlen);
1440       abort();
1441   }
1442 }
1443
1444 uint32_t gdbserver_t::dr_read32(unsigned int index)
1445 {
1446   uint32_t value = sim->debug_module.ram_read32(index);
1447   D(fprintf(stderr, "read32(%d) -> 0x%x\n", index, value));
1448   return value;
1449 }
1450
1451 uint64_t gdbserver_t::dr_read64(unsigned int index)
1452 {
1453   return ((uint64_t) dr_read32(index+1) << 32) | dr_read32(index);
1454 }
1455
1456 uint64_t gdbserver_t::dr_read(enum slot slot)
1457 {
1458   switch (xlen) {
1459     case 32:
1460       return dr_read32(slot_offset32[slot]);
1461     case 64:
1462       return dr_read64(slot_offset64[slot]);
1463     case 128:
1464       abort();
1465     default:
1466       abort();
1467   }
1468 }
1469
1470 void gdbserver_t::add_operation(operation_t* operation)
1471 {
1472   operation_queue.push(operation);
1473 }
1474
1475 void gdbserver_t::accept()
1476 {
1477   client_fd = ::accept(socket_fd, NULL, NULL);
1478   if (client_fd == -1) {
1479     if (errno == EAGAIN) {
1480       // No client waiting to connect right now.
1481     } else {
1482       fprintf(stderr, "failed to accept on socket: %s (%d)\n", strerror(errno),
1483           errno);
1484       abort();
1485     }
1486   } else {
1487     fcntl(client_fd, F_SETFL, O_NONBLOCK);
1488
1489     expect_ack = false;
1490     extended_mode = false;
1491
1492     // gdb wants the core to be halted when it attaches.
1493     add_operation(new halt_op_t(*this));
1494   }
1495 }
1496
1497 void gdbserver_t::read()
1498 {
1499   // Reading from a non-blocking socket still blocks if there is no data
1500   // available.
1501
1502   size_t count = recv_buf.contiguous_empty_size();
1503   assert(count > 0);
1504   ssize_t bytes = ::read(client_fd, recv_buf.contiguous_empty(), count);
1505   if (bytes == -1) {
1506     if (errno == EAGAIN) {
1507       // We'll try again the next call.
1508     } else {
1509       fprintf(stderr, "failed to read on socket: %s (%d)\n", strerror(errno), errno);
1510       abort();
1511     }
1512   } else if (bytes == 0) {
1513     // The remote disconnected.
1514     client_fd = 0;
1515     processor_t *p = sim->get_core(0);
1516     // TODO p->set_halted(false, HR_NONE);
1517     recv_buf.reset();
1518     send_buf.reset();
1519   } else {
1520     recv_buf.data_added(bytes);
1521   }
1522 }
1523
1524 void gdbserver_t::write()
1525 {
1526   if (send_buf.empty())
1527     return;
1528
1529   while (!send_buf.empty()) {
1530     unsigned int count = send_buf.contiguous_data_size();
1531     assert(count > 0);
1532     ssize_t bytes = ::write(client_fd, send_buf.contiguous_data(), count);
1533     if (bytes == -1) {
1534       fprintf(stderr, "failed to write to socket: %s (%d)\n", strerror(errno), errno);
1535       abort();
1536     } else if (bytes == 0) {
1537       // Client can't take any more data right now.
1538       break;
1539     } else {
1540       D(fprintf(stderr, "wrote %ld bytes: ", bytes));
1541       for (unsigned int i = 0; i < bytes; i++) {
1542         D(fprintf(stderr, "%c", send_buf[i]));
1543       }
1544       D(fprintf(stderr, "\n"));
1545       send_buf.consume(bytes);
1546     }
1547   }
1548 }
1549
1550 void print_packet(const std::vector<uint8_t> &packet)
1551 {
1552   for (uint8_t c : packet) {
1553     if (c >= ' ' and c <= '~')
1554       fprintf(stderr, "%c", c);
1555     else
1556       fprintf(stderr, "\\x%02x", c);
1557   }
1558   fprintf(stderr, "\n");
1559 }
1560
1561 uint8_t compute_checksum(const std::vector<uint8_t> &packet)
1562 {
1563   uint8_t checksum = 0;
1564   for (auto i = packet.begin() + 1; i != packet.end() - 3; i++ ) {
1565     checksum += *i;
1566   }
1567   return checksum;
1568 }
1569
1570 uint8_t character_hex_value(uint8_t character)
1571 {
1572   if (character >= '0' && character <= '9')
1573     return character - '0';
1574   if (character >= 'a' && character <= 'f')
1575     return 10 + character - 'a';
1576   if (character >= 'A' && character <= 'F')
1577     return 10 + character - 'A';
1578   return 0xff;
1579 }
1580
1581 uint8_t extract_checksum(const std::vector<uint8_t> &packet)
1582 {
1583   return character_hex_value(*(packet.end() - 1)) +
1584     16 * character_hex_value(*(packet.end() - 2));
1585 }
1586
1587 void gdbserver_t::process_requests()
1588 {
1589   // See https://sourceware.org/gdb/onlinedocs/gdb/Remote-Protocol.html
1590
1591   while (!recv_buf.empty()) {
1592     std::vector<uint8_t> packet;
1593     for (unsigned int i = 0; i < recv_buf.size(); i++) {
1594       uint8_t b = recv_buf[i];
1595
1596       if (packet.empty() && expect_ack && b == '+') {
1597         recv_buf.consume(1);
1598         break;
1599       }
1600
1601       if (packet.empty() && b == 3) {
1602         D(fprintf(stderr, "Received interrupt\n"));
1603         recv_buf.consume(1);
1604         handle_interrupt();
1605         break;
1606       }
1607
1608       if (b == '$') {
1609         // Start of new packet.
1610         if (!packet.empty()) {
1611           fprintf(stderr, "Received malformed %ld-byte packet from debug client: ",
1612               packet.size());
1613           print_packet(packet);
1614           recv_buf.consume(i);
1615           break;
1616         }
1617       }
1618
1619       packet.push_back(b);
1620
1621       // Packets consist of $<packet-data>#<checksum>
1622       // where <checksum> is
1623       if (packet.size() >= 4 &&
1624           packet[packet.size()-3] == '#') {
1625         handle_packet(packet);
1626         recv_buf.consume(i+1);
1627         break;
1628       }
1629     }
1630     // There's a partial packet in the buffer. Wait until we get more data to
1631     // process it.
1632     if (packet.size()) {
1633       break;
1634     }
1635   }
1636 }
1637
1638 void gdbserver_t::handle_halt_reason(const std::vector<uint8_t> &packet)
1639 {
1640   send_packet("S00");
1641 }
1642
1643 void gdbserver_t::handle_general_registers_read(const std::vector<uint8_t> &packet)
1644 {
1645   add_operation(new general_registers_read_op_t(*this));
1646 }
1647
1648 void gdbserver_t::set_interrupt(uint32_t hartid) {
1649   sim->debug_module.set_interrupt(hartid);
1650 }
1651
1652 // First byte is the most-significant one.
1653 // Eg. "08675309" becomes 0x08675309.
1654 uint64_t consume_hex_number(std::vector<uint8_t>::const_iterator &iter,
1655     std::vector<uint8_t>::const_iterator end)
1656 {
1657   uint64_t value = 0;
1658
1659   while (iter != end) {
1660     uint8_t c = *iter;
1661     uint64_t c_value = character_hex_value(c);
1662     if (c_value > 15)
1663       break;
1664     iter++;
1665     value <<= 4;
1666     value += c_value;
1667   }
1668   return value;
1669 }
1670
1671 // First byte is the least-significant one.
1672 // Eg. "08675309" becomes 0x09536708
1673 uint64_t consume_hex_number_le(std::vector<uint8_t>::const_iterator &iter,
1674     std::vector<uint8_t>::const_iterator end)
1675 {
1676   uint64_t value = 0;
1677   unsigned int shift = 4;
1678
1679   while (iter != end) {
1680     uint8_t c = *iter;
1681     uint64_t c_value = character_hex_value(c);
1682     if (c_value > 15)
1683       break;
1684     iter++;
1685     value |= c_value << shift;
1686     if ((shift % 8) == 0)
1687       shift += 12;
1688     else
1689       shift -= 4;
1690   }
1691   return value;
1692 }
1693
1694 void consume_string(std::string &str, std::vector<uint8_t>::const_iterator &iter,
1695     std::vector<uint8_t>::const_iterator end, uint8_t separator)
1696 {
1697   while (iter != end && *iter != separator) {
1698     str.append(1, (char) *iter);
1699     iter++;
1700   }
1701 }
1702
1703 void gdbserver_t::handle_register_read(const std::vector<uint8_t> &packet)
1704 {
1705   // p n
1706
1707   std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1708   unsigned int n = consume_hex_number(iter, packet.end());
1709   if (*iter != '#')
1710     return send_packet("E01");
1711
1712   add_operation(new register_read_op_t(*this, n));
1713 }
1714
1715 void gdbserver_t::handle_register_write(const std::vector<uint8_t> &packet)
1716 {
1717   // P n...=r...
1718
1719   std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1720   unsigned int n = consume_hex_number(iter, packet.end());
1721   if (*iter != '=')
1722     return send_packet("E05");
1723   iter++;
1724
1725   reg_t value = consume_hex_number_le(iter, packet.end());
1726   if (*iter != '#')
1727     return send_packet("E06");
1728
1729   processor_t *p = sim->get_core(0);
1730
1731   add_operation(new register_write_op_t(*this, n, value));
1732
1733   return send_packet("OK");
1734 }
1735
1736 void gdbserver_t::handle_memory_read(const std::vector<uint8_t> &packet)
1737 {
1738   // m addr,length
1739   std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1740   reg_t address = consume_hex_number(iter, packet.end());
1741   if (*iter != ',')
1742     return send_packet("E10");
1743   iter++;
1744   reg_t length = consume_hex_number(iter, packet.end());
1745   if (*iter != '#')
1746     return send_packet("E11");
1747
1748   add_operation(new collect_translation_info_op_t(*this, address, length));
1749   add_operation(new memory_read_op_t(*this, address, length));
1750 }
1751
1752 void gdbserver_t::handle_memory_binary_write(const std::vector<uint8_t> &packet)
1753 {
1754   // X addr,length:XX...
1755   std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1756   reg_t address = consume_hex_number(iter, packet.end());
1757   if (*iter != ',')
1758     return send_packet("E20");
1759   iter++;
1760   reg_t length = consume_hex_number(iter, packet.end());
1761   if (*iter != ':')
1762     return send_packet("E21");
1763   iter++;
1764
1765   if (length == 0) {
1766     return send_packet("OK");
1767   }
1768
1769   unsigned char *data = new unsigned char[length];
1770   for (unsigned int i = 0; i < length; i++) {
1771     if (iter == packet.end()) {
1772       return send_packet("E22");
1773     }
1774     uint8_t c = *iter;
1775     iter++;
1776     if (c == '}') {
1777       // The binary data representation uses 7d (ascii ‘}’) as an escape
1778       // character. Any escaped byte is transmitted as the escape character
1779       // followed by the original character XORed with 0x20. For example, the
1780       // byte 0x7d would be transmitted as the two bytes 0x7d 0x5d. The bytes
1781       // 0x23 (ascii ‘#’), 0x24 (ascii ‘$’), and 0x7d (ascii ‘}’) must always
1782       // be escaped.
1783       if (iter == packet.end()) {
1784         return send_packet("E23");
1785       }
1786       c = (*iter) ^ 0x20;
1787       iter++;
1788     }
1789     data[i] = c;
1790   }
1791   if (*iter != '#')
1792     return send_packet("E4b"); // EOVERFLOW
1793
1794   add_operation(new collect_translation_info_op_t(*this, address, length));
1795   add_operation(new memory_write_op_t(*this, address, length, data));
1796 }
1797
1798 void gdbserver_t::handle_continue(const std::vector<uint8_t> &packet)
1799 {
1800   // c [addr]
1801   processor_t *p = sim->get_core(0);
1802   if (packet[2] != '#') {
1803     std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1804     dpc = consume_hex_number(iter, packet.end());
1805     if (*iter != '#')
1806       return send_packet("E30");
1807   }
1808
1809   add_operation(new maybe_restore_tselect_op_t(*this));
1810   add_operation(new continue_op_t(*this, false));
1811 }
1812
1813 void gdbserver_t::handle_step(const std::vector<uint8_t> &packet)
1814 {
1815   // s [addr]
1816   if (packet[2] != '#') {
1817     std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1818     die("handle_step");
1819     //p->state.pc = consume_hex_number(iter, packet.end());
1820     if (*iter != '#')
1821       return send_packet("E40");
1822   }
1823
1824   add_operation(new maybe_restore_tselect_op_t(*this));
1825   add_operation(new continue_op_t(*this, true));
1826 }
1827
1828 void gdbserver_t::handle_kill(const std::vector<uint8_t> &packet)
1829 {
1830   // k
1831   // The exact effect of this packet is not specified.
1832   // Looks like OpenOCD disconnects?
1833   // TODO
1834 }
1835
1836 void gdbserver_t::handle_extended(const std::vector<uint8_t> &packet)
1837 {
1838   // Enable extended mode. In extended mode, the remote server is made
1839   // persistent. The ‘R’ packet is used to restart the program being debugged.
1840   send_packet("OK");
1841   extended_mode = true;
1842 }
1843
1844 void gdbserver_t::software_breakpoint_insert(reg_t vaddr, unsigned int size)
1845 {
1846   fence_i_required = true;
1847   add_operation(new collect_translation_info_op_t(*this, vaddr, size));
1848   unsigned char* inst = new unsigned char[4];
1849   if (size == 2) {
1850     inst[0] = C_EBREAK & 0xff;
1851     inst[1] = (C_EBREAK >> 8) & 0xff;
1852   } else {
1853     inst[0] = EBREAK & 0xff;
1854     inst[1] = (EBREAK >> 8) & 0xff;
1855     inst[2] = (EBREAK >> 16) & 0xff;
1856     inst[3] = (EBREAK >> 24) & 0xff;
1857   }
1858
1859   software_breakpoint_t bp = {
1860     .vaddr = vaddr,
1861     .size = size
1862   };
1863   software_breakpoints[vaddr] = bp;
1864   add_operation(new memory_read_op_t(*this, bp.vaddr, bp.size,
1865         software_breakpoints[bp.vaddr].instruction));
1866   add_operation(new memory_write_op_t(*this, bp.vaddr, bp.size, inst));
1867 }
1868
1869 void gdbserver_t::software_breakpoint_remove(reg_t vaddr, unsigned int size)
1870 {
1871   fence_i_required = true;
1872   add_operation(new collect_translation_info_op_t(*this, vaddr, size));
1873
1874   software_breakpoint_t found_bp = software_breakpoints[vaddr];
1875   unsigned char* instruction = new unsigned char[4];
1876   memcpy(instruction, found_bp.instruction, 4);
1877   add_operation(new memory_write_op_t(*this, found_bp.vaddr,
1878         found_bp.size, instruction));
1879   software_breakpoints.erase(vaddr);
1880 }
1881
1882 void gdbserver_t::hardware_breakpoint_insert(const hardware_breakpoint_t &bp)
1883 {
1884   add_operation(new maybe_save_tselect_op_t(*this));
1885   add_operation(new hardware_breakpoint_insert_op_t(*this, bp));
1886 }
1887
1888 void gdbserver_t::hardware_breakpoint_remove(const hardware_breakpoint_t &bp)
1889 {
1890   add_operation(new maybe_save_tselect_op_t(*this));
1891   hardware_breakpoint_t found = *hardware_breakpoints.find(bp);
1892   add_operation(new hardware_breakpoint_remove_op_t(*this, found));
1893 }
1894
1895 void gdbserver_t::handle_breakpoint(const std::vector<uint8_t> &packet)
1896 {
1897   // insert: Z type,addr,length
1898   // remove: z type,addr,length
1899
1900   // type: 0 - software breakpoint, 1 - hardware breakpoint, 2 - write
1901   // watchpoint, 3 - read watchpoint, 4 - access watchpoint; addr is address;
1902   // length is in bytes. For a software breakpoint, length specifies the size
1903   // of the instruction to be patched. For hardware breakpoints and watchpoints
1904   // length specifies the memory region to be monitored. To avoid potential
1905   // problems with duplicate packets, the operations should be implemented in
1906   // an idempotent way.
1907
1908   bool insert = (packet[1] == 'Z');
1909   std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1910   gdb_breakpoint_type_t type = static_cast<gdb_breakpoint_type_t>(
1911       consume_hex_number(iter, packet.end()));
1912   if (*iter != ',')
1913     return send_packet("E50");
1914   iter++;
1915   reg_t address = consume_hex_number(iter, packet.end());
1916   if (*iter != ',')
1917     return send_packet("E51");
1918   iter++;
1919   unsigned int size = consume_hex_number(iter, packet.end());
1920   // There may be more options after a ; here, but we don't support that.
1921   if (*iter != '#')
1922     return send_packet("E52");
1923
1924   switch (type) {
1925     case GB_SOFTWARE:
1926       if (size != 2 && size != 4) {
1927         return send_packet("E53");
1928       }
1929       if (insert) {
1930         software_breakpoint_insert(address, size);
1931       } else {
1932         software_breakpoint_remove(address, size);
1933       }
1934       break;
1935
1936     case GB_HARDWARE:
1937     case GB_WRITE:
1938     case GB_READ:
1939     case GB_ACCESS:
1940       {
1941         hardware_breakpoint_t bp = {
1942           .vaddr = address,
1943           .size = size
1944         };
1945         bp.load = (type == GB_READ || type == GB_ACCESS);
1946         bp.store = (type == GB_WRITE || type == GB_ACCESS);
1947         bp.execute = (type == GB_HARDWARE || type == GB_ACCESS);
1948         if (insert) {
1949           hardware_breakpoint_insert(bp);
1950           // Insert might fail if there's no space, so the insert operation will
1951           // send its own OK (or not).
1952           return;
1953         } else {
1954           hardware_breakpoint_remove(bp);
1955         }
1956       }
1957       break;
1958
1959     default:
1960       return send_packet("E56");
1961   }
1962
1963   return send_packet("OK");
1964 }
1965
1966 void gdbserver_t::handle_query(const std::vector<uint8_t> &packet)
1967 {
1968   std::string name;
1969   std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1970
1971   consume_string(name, iter, packet.end(), ':');
1972   if (iter != packet.end())
1973     iter++;
1974   if (name == "Supported") {
1975     start_packet();
1976     while (iter != packet.end()) {
1977       std::string feature;
1978       consume_string(feature, iter, packet.end(), ';');
1979       if (iter != packet.end())
1980         iter++;
1981       if (feature == "swbreak+") {
1982         send("swbreak+;");
1983       }
1984     }
1985     send("PacketSize=131072;");
1986     return end_packet();
1987   }
1988
1989   D(fprintf(stderr, "Unsupported query %s\n", name.c_str()));
1990   return send_packet("");
1991 }
1992
1993 void gdbserver_t::handle_packet(const std::vector<uint8_t> &packet)
1994 {
1995   if (compute_checksum(packet) != extract_checksum(packet)) {
1996     fprintf(stderr, "Received %ld-byte packet with invalid checksum\n", packet.size());
1997     fprintf(stderr, "Computed checksum: %x\n", compute_checksum(packet));
1998     print_packet(packet);
1999     send("-");
2000     return;
2001   }
2002
2003   D(fprintf(stderr, "Received %ld-byte packet from debug client: ", packet.size()));
2004   D(print_packet(packet));
2005   send("+");
2006
2007   switch (packet[1]) {
2008     case '!':
2009       return handle_extended(packet);
2010     case '?':
2011       return handle_halt_reason(packet);
2012     case 'g':
2013       return handle_general_registers_read(packet);
2014 //    case 'k':
2015 //      return handle_kill(packet);
2016     case 'm':
2017       return handle_memory_read(packet);
2018 //    case 'M':
2019 //      return handle_memory_write(packet);
2020     case 'X':
2021       return handle_memory_binary_write(packet);
2022     case 'p':
2023       return handle_register_read(packet);
2024     case 'P':
2025       return handle_register_write(packet);
2026     case 'c':
2027       return handle_continue(packet);
2028     case 's':
2029       return handle_step(packet);
2030     case 'z':
2031     case 'Z':
2032       return handle_breakpoint(packet);
2033     case 'q':
2034     case 'Q':
2035       return handle_query(packet);
2036   }
2037
2038   // Not supported.
2039   D(fprintf(stderr, "** Unsupported packet: "));
2040   D(print_packet(packet));
2041   send_packet("");
2042 }
2043
2044 void gdbserver_t::handle_interrupt()
2045 {
2046   processor_t *p = sim->get_core(0);
2047   add_operation(new halt_op_t(*this, true));
2048 }
2049
2050 void gdbserver_t::handle()
2051 {
2052   if (client_fd > 0) {
2053     processor_t *p = sim->get_core(0);
2054
2055     bool interrupt = sim->debug_module.get_interrupt(0);
2056
2057     if (!interrupt && !operation_queue.empty()) {
2058       operation_t *operation = operation_queue.front();
2059       if (operation->step()) {
2060         operation_queue.pop();
2061         delete operation;
2062       }
2063     }
2064
2065     bool halt_notification = sim->debug_module.get_halt_notification(0);
2066     if (halt_notification) {
2067       sim->debug_module.clear_halt_notification(0);
2068       add_operation(new halt_op_t(*this, true));
2069     }
2070
2071     this->read();
2072     this->write();
2073
2074   } else {
2075     this->accept();
2076   }
2077
2078   if (operation_queue.empty()) {
2079     this->process_requests();
2080   }
2081 }
2082
2083 void gdbserver_t::send(const char* msg)
2084 {
2085   unsigned int length = strlen(msg);
2086   for (const char *c = msg; *c; c++)
2087     running_checksum += *c;
2088   send_buf.append((const uint8_t *) msg, length);
2089 }
2090
2091 void gdbserver_t::send(uint64_t value)
2092 {
2093   char buffer[3];
2094   for (unsigned int i = 0; i < 8; i++) {
2095     sprintf(buffer, "%02x", (int) (value & 0xff));
2096     send(buffer);
2097     value >>= 8;
2098   }
2099 }
2100
2101 void gdbserver_t::send(uint32_t value)
2102 {
2103   char buffer[3];
2104   for (unsigned int i = 0; i < 4; i++) {
2105     sprintf(buffer, "%02x", (int) (value & 0xff));
2106     send(buffer);
2107     value >>= 8;
2108   }
2109 }
2110
2111 void gdbserver_t::send(uint8_t value)
2112 {
2113   char buffer[3];
2114   sprintf(buffer, "%02x", (int) value);
2115   send(buffer);
2116 }
2117
2118 void gdbserver_t::send_packet(const char* data)
2119 {
2120   start_packet();
2121   send(data);
2122   end_packet();
2123   expect_ack = true;
2124 }
2125
2126 void gdbserver_t::start_packet()
2127 {
2128   send("$");
2129   running_checksum = 0;
2130 }
2131
2132 void gdbserver_t::end_packet(const char* data)
2133 {
2134   if (data) {
2135     send(data);
2136   }
2137
2138   char checksum_string[4];
2139   sprintf(checksum_string, "#%02x", running_checksum);
2140   send(checksum_string);
2141   expect_ack = true;
2142 }