check if register redirection is active, and if vectorisation enabled
[riscv-isa-sim.git] / riscv / insn_template_sv.cc
1 // See LICENSE for license details.
2
3 reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
4 {
5 int xlen = ISASZ;
6 reg_t npc = sext_xlen(pc + insn_length(INSNCODE));
7 // messy way to do it: insn_t is used elsewhere in a union,
8 // so a workaround is to grab the bits from the insn_t
9 // and create an sv-variant. also an opportunity to pass
10 // in the loop index (voffs) which will be added on to
11 // any registers that are marked as "vectorised"
12 insn_bits_t bits = s_insn.bits();
13 #ifndef USING_NOREGS
14 int voffs = 0;
15 int vlen = 1;
16 sv_insn_t insn(bits, voffs);
17 bool vectorop = false;
18 reg_t predicate = 0;
19 // identify which regs have had their CSR entries set as vectorised.
20 // really could do with a macro for-loop here... oh well...
21 // integer ops, RD, RS1, RS2, RS3 (use sv_int_tb)
22 #ifdef USING_RD
23 vectorop &= check_reg(true, s_insn.rd());
24 #endif
25 #ifdef USING_RS1
26 vectorop &= check_reg(true, s_insn.rs1());
27 #endif
28 #ifdef USING_RS2
29 vectorop &= check_reg(true, s_insn.rs2());
30 #endif
31 #ifdef USING_RS2
32 vectorop &= check_reg(true, s_insn.rs3());
33 #endif
34 // fp ops, RD, RS1, RS2, RS3 (use sv_fp_tb)
35 #ifdef USING_FRD
36 vectorop &= check_reg(false, s_insn.frd());
37 #endif
38 #ifdef USING_FRS1
39 vectorop &= check_reg(false, s_insn.frs1());
40 #endif
41 #ifdef USING_FRS2
42 vectorop &= check_reg(false, s_insn.rs2());
43 #endif
44 #ifdef USING_FRS2
45 vectorop &= check_reg(false, s_insn.rs3());
46 #endif
47
48 // if vectorop is set, one of the regs is not a scalar,
49 // so we must read the VL CSR and do a loop
50 if (vectorop)
51 {
52 // TODO: vlen = p->CSR(SIMPLEV_VL); // something like that...
53 }
54 for (; voffs < vlen; voffs++)
55 {
56 #include INCLUDEFILE
57 }
58 #else
59 insn_t insn(bits);
60 #include INCLUDEFILE
61 #endif
62 trace_opcode(p, INSNCODE, insn);
63 return npc;
64 }
65