riscv/insn_template_sv.cc

   1 // See LICENSE for license details.
   2
   3 #define xstr(s) str(s)
   4 #define str(s) #s
   5
   6 reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
   7 {
   8   int xlen = ISASZ;
   9   reg_t npc = sext_xlen(pc + insn_length(INSNCODE));
  10   // messy way to do it: insn_t is used elsewhere in a union,
  11   // so a workaround is to grab the bits from the insn_t
  12   // and create an sv-variant.  also an opportunity to pass
  13   // in the loop index (voffs) which will be added on to
  14   // any registers that are marked as "vectorised"
  15   insn_bits_t bits = s_insn.bits();
  16 #ifndef USING_NOREGS
  17   int vlen = p->get_state()->vl;
  18   // need to know if register is used as float or int.
  19   // REGS_PATTERN is generated by id_regs.py (per opcode)
  20   unsigned int floatintmap = REGS_PATTERN;
  21   reg_t dest_pred = ~0x0;
  22   sv_insn_t insn(p, bits, floatintmap,
  23                  dest_pred, dest_pred, dest_pred, dest_pred);
  24   bool zeroing;
  25 #if defined(USING_REG_RD) || defined(USING_REG_FRD)
  26   // use the ORIGINAL, i.e. NON-REDIRECTED, register here
  27   dest_pred = insn.predicate(s_insn.rd(), floatintmap & REG_RD, zeroing);
  28 #endif
  29   // identify which regs have had their CSR entries set as vectorised.
  30   // really could do with a macro for-loop here... oh well...
  31   // integer ops, RD, RS1, RS2, RS3 (use sv_int_tb)
  32   if (insn.sv_check_reg(true, 16))
  33   {
  34     fprintf(stderr, "reg %s %x rd %ld rs1 %ld rs2 %ld vlen %d\n",
  35             xstr(INSN), INSNCODE, s_insn.rd(), s_insn.rs1(), s_insn.rs2(),
  36             vlen);
  37   }
  38   // if vectorop is set, one of the regs is not a scalar,
  39   // so we must read the VL CSR and do a loop
  40   if (vlen == 0)
  41   {
  42     vlen = 1; // minimum of one loop
  43   }
  44   for (int voffs=0; voffs < vlen; voffs++)
  45   {
  46       insn.reset_vloop_check();
  47       #include INCLUDEFILE
  48 #if defined(USING_REG_RD) || defined(USING_REG_FRD)
  49       if (zeroing && ((dest_pred & (1<<voffs)) == 0))
  50       {
  51           WRITE_REG(insn._rd(), 0);
  52       }
  53 #endif
  54       if (vlen > 1)
  55       {
  56         fprintf(stderr, "reg %s %x vloop %d vlen %d stop %d pred %lx\n",
  57                 xstr(INSN), INSNCODE, voffs, vlen, insn.stop_vloop(),
  58                 dest_pred & (1<<voffs));
  59       }
  60       insn.reset_caches(); // ready to increment offsets in next iteration
  61       if (insn.stop_vloop())
  62       {
  63         break;
  64       }
  65   }
  66 #else
  67   insn_t insn(bits);
  68   #include INCLUDEFILE
  69 #endif
  70   trace_opcode(p, INSNCODE, insn);
  71   return npc;
  72 }
  73