shuffle things around a bit for sv, put rv32/64_name back to like they were
[riscv-isa-sim.git] / riscv / insn_template_sv.cc
1 // See LICENSE for license details.
2
3 reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
4 {
5 int xlen = ISASZ;
6 reg_t npc = sext_xlen(pc + insn_length(INSNCODE));
7 insn_bits_t bits = s_insn.bits();
8 int voffs = 0;
9 sv_insn_t insn(bits, voffs);
10 #include INCLUDEFILE
11 trace_opcode(p, INSNCODE, s_insn);
12 return npc;
13 }
14