riscv/insn_template_sv.cc

   1 // See LICENSE for license details.
   2
   3 #define xstr(s) str(s)
   4 #define str(s) #s
   5
   6 reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
   7 {
   8   int xlen = ISASZ;
   9   reg_t npc = sext_xlen(pc + insn_length(INSNCODE));
  10   // messy way to do it: insn_t is used elsewhere in a union,
  11   // so cannot create virtual functions.
  12   // a workaround is to grab the bits from the insn_t
  13   // and create an sv-variant.  also an opportunity to pass
  14   // in a stack of other things that are needed.
  15   insn_bits_t bits = s_insn.bits();
  16 #ifndef USING_NOREGS
  17   int vlen = p->get_state()->vl;
  18   // need to know if register is used as float or int.
  19   // REGS_PATTERN is generated by id_regs.py (per opcode)
  20   unsigned int floatintmap = REGS_PATTERN;
  21   reg_t dest_pred = ~0x0;
  22   bool ldimm_sv = false;
  23 #ifdef INSN_TYPE_LOAD
  24   bool ldimm_sv = true;
  25 #endif
  26   sv_insn_t insn(p, bits, floatintmap,
  27                  dest_pred, dest_pred, dest_pred, dest_pred,
  28                  ldimm_sv);
  29   bool zeroing;
  30 #if defined(USING_REG_RD) || defined(USING_REG_FRD)
  31   // use the ORIGINAL, i.e. NON-REDIRECTED, register here
  32   dest_pred = insn.predicate(s_insn.rd(), floatintmap & REG_RD, zeroing);
  33 #endif
  34   // identify which regs have had their CSR entries set as vectorised.
  35   // really could do with a macro for-loop here... oh well...
  36   // integer ops, RD, RS1, RS2, RS3 (use sv_int_tb)
  37   if (insn.sv_check_reg(true, 16))
  38   {
  39     fprintf(stderr, "reg %s %x rd %ld rs1 %ld rs2 %ld vlen %d\n",
  40             xstr(INSN), INSNCODE, s_insn.rd(), s_insn.rs1(), s_insn.rs2(),
  41             vlen);
  42   }
  43   // if vectorop is set, one of the regs is not a scalar,
  44   // so we must read the VL CSR and do a loop
  45   if (vlen == 0)
  46   {
  47     vlen = 1; // minimum of one loop
  48   }
  49   for (int voffs=0; voffs < vlen; voffs++)
  50   {
  51       insn.reset_vloop_check();
  52       #include INCLUDEFILE
  53 #if defined(USING_REG_RD) || defined(USING_REG_FRD)
  54       // don't check inversion here as dest_pred has already been inverted
  55       if (zeroing && ((dest_pred & (1<<voffs)) == 0))
  56       {
  57           // insn._rd() would be predicated: have to use insn._rd() here
  58           WRITE_REG(insn._rd(), 0);
  59       }
  60 #endif
  61       if (vlen > 1)
  62       {
  63 #if defined(USING_REG_RD)
  64         fprintf(stderr, "reg %s %x vloop %d vlen %d stop %d pred %lx rd%lx\n",
  65                 xstr(INSN), INSNCODE, voffs, vlen, insn.stop_vloop(),
  66                 dest_pred & (1<<voffs), READ_REG(insn._rd()));
  67 #endif
  68 #if defined(USING_REG_FRD)
  69         fprintf(stderr, "reg %s %x vloop %d vlen %d stop %d pred %lx rd%lx\n",
  70                 xstr(INSN), INSNCODE, voffs, vlen, insn.stop_vloop(),
  71                 dest_pred & (1<<voffs),
  72                 (READ_FREG(insn._rd())));
  73 #endif
  74       }
  75       insn.reset_caches(); // ready to increment offsets in next iteration
  76       if (insn.stop_vloop())
  77       {
  78         break;
  79       }
  80   }
  81 #else
  82   insn_t insn(bits);
  83   #include INCLUDEFILE
  84 #endif
  85   trace_opcode(p, INSNCODE, insn);
  86   return npc;
  87 }
  88