riscv/insn_template_sv.cc

   1 // See LICENSE for license details.
   2
   3 reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
   4 {
   5   int xlen = ISASZ;
   6   reg_t npc = sext_xlen(pc + insn_length(INSNCODE));
   7   // messy way to do it: insn_t is used elsewhere in a union,
   8   // so a workaround is to grab the bits from the insn_t
   9   // and create an sv-variant.  also an opportunity to pass
  10   // in the loop index (voffs) which will be added on to
  11   // any registers that are marked as "vectorised"
  12   insn_bits_t bits = s_insn.bits();
  13 #ifndef USING_NOREGS
  14   int voffs = 0;
  15   int vlen = 1;
  16   sv_insn_t insn(bits, voffs);
  17   bool vectorop = false;
  18   for (; voffs < vlen; voffs++)
  19   {
  20       #include INCLUDEFILE
  21   }
  22 #else
  23   insn_t insn(bits);
  24   #include INCLUDEFILE
  25 #endif
  26   trace_opcode(p, INSNCODE, insn);
  27   return npc;
  28 }
  29