riscv/insn_template_sv.cc

   1 // See LICENSE for license details.
   2
   3 #define xstr(s) str(s)
   4 #define str(s) #s
   5
   6 reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
   7 {
   8   int xlen = ISASZ;
   9   reg_t npc = sext_xlen(pc + insn_length(INSNCODE));
  10   // messy way to do it: insn_t is used elsewhere in a union,
  11   // so a workaround is to grab the bits from the insn_t
  12   // and create an sv-variant.  also an opportunity to pass
  13   // in the loop index (voffs) which will be added on to
  14   // any registers that are marked as "vectorised"
  15   insn_bits_t bits = s_insn.bits();
  16 #ifndef USING_NOREGS
  17   int vlen = p->get_state()->vl;
  18   // need to know if register is used as float or int.
  19   // REGS_PATTERN is generated by id_regs.py (per opcode)
  20   unsigned int floatintmap = REGS_PATTERN;
  21   reg_t predicate = 0;
  22   sv_insn_t insn(p, bits, floatintmap,
  23                  predicate, predicate, predicate, predicate);
  24   // identify which regs have had their CSR entries set as vectorised.
  25   // really could do with a macro for-loop here... oh well...
  26   // integer ops, RD, RS1, RS2, RS3 (use sv_int_tb)
  27   if (insn.sv_check_reg(true, 16))
  28   {
  29     fprintf(stderr, "reg %s %x rd %ld rs1 %ld rs2 %ld vlen %d\n",
  30             xstr(INSN), INSNCODE, s_insn.rd(), s_insn.rs1(), s_insn.rs2(),
  31             vlen);
  32   }
  33   // if vectorop is set, one of the regs is not a scalar,
  34   // so we must read the VL CSR and do a loop
  35   if (vlen == 0)
  36   {
  37     vlen = 1; // minimum of one loop
  38   }
  39   for (int voffs=0; voffs < vlen; voffs++)
  40   {
  41       insn.reset_vloop_check();
  42       #include INCLUDEFILE
  43       if (vlen > 1)
  44       {
  45         fprintf(stderr, "reg %s %x vloop %d vlen %d stop %d\n",
  46                 xstr(INSN), INSNCODE, voffs, vlen, insn.stop_vloop());
  47       }
  48       insn.reset_caches(); // ready to increment offsets in next iteration
  49       if (insn.stop_vloop())
  50       {
  51         break;
  52       }
  53   }
  54 #else
  55   insn_t insn(bits);
  56   #include INCLUDEFILE
  57 #endif
  58   trace_opcode(p, INSNCODE, insn);
  59   return npc;
  60 }
  61