riscv/insn_template_sv.cc

   1 // See LICENSE for license details.
   2
   3 reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
   4 {
   5   int xlen = ISASZ;
   6   reg_t npc = sext_xlen(pc + insn_length(INSNCODE));
   7   // messy way to do it: insn_t is used elsewhere in a union,
   8   // so a workaround is to grab the bits from the insn_t
   9   // and create an sv-variant.  also an opportunity to pass
  10   // in the loop index (voffs) which will be added on to
  11   // any registers that are marked as "vectorised"
  12   insn_bits_t bits = s_insn.bits();
  13 #ifndef USING_NOREGS
  14   int vlen = 1;
  15   // need to know if register is used as float or int.
  16   // REGS_PATTERN is generated by id_regs.py (per opcode)
  17   unsigned int floatintmap = REGS_PATTERN;
  18   sv_insn_t insn(p, bits, floatintmap);
  19   reg_t predicate = 0;
  20   // identify which regs have had their CSR entries set as vectorised.
  21   // really could do with a macro for-loop here... oh well...
  22   // integer ops, RD, RS1, RS2, RS3 (use sv_int_tb)
  23   bool vectorop =
  24 #ifdef USING_RD
  25   insn.check_reg(true, s_insn.rd()) |
  26 #endif
  27 #ifdef USING_RS1
  28   insn.check_reg(true, s_insn.rs1()) |
  29 #endif
  30 #ifdef USING_RS2
  31   insn.check_reg(true, s_insn.rs2()) |
  32 #endif
  33 #ifdef USING_RS2
  34  insn.check_reg(true, s_insn.rs3()) |
  35 #endif
  36   // fp ops, RD, RS1, RS2, RS3 (use sv_fp_tb)
  37 #ifdef USING_FRD
  38   insn.check_reg(false, s_insn.frd()) |
  39 #endif
  40 #ifdef USING_FRS1
  41   insn.check_reg(false, s_insn.frs1()) |
  42 #endif
  43 #ifdef USING_FRS2
  44   insn.check_reg(false, s_insn.rs2()) |
  45 #endif
  46 #ifdef USING_FRS2
  47   insn.check_reg(false, s_insn.rs3()) |
  48 #endif
  49   false; // save a few cycles by |ing the checks together.
  50
  51   // if vectorop is set, one of the regs is not a scalar,
  52   // so we must read the VL CSR and do a loop
  53   if (vectorop)
  54   {
  55     // TODO: vlen = p->CSR(SIMPLEV_VL); // something like that...
  56   }
  57   for (int voffs=0; voffs < vlen; voffs++)
  58   {
  59       #include INCLUDEFILE
  60       insn.reset_caches(); // ready to increment offsets in next iteration
  61   }
  62 #else
  63   insn_t insn(bits);
  64   #include INCLUDEFILE
  65 #endif
  66   trace_opcode(p, INSNCODE, insn);
  67   return npc;
  68 }
  69