Move towards RVC v1.8
[riscv-isa-sim.git] / riscv / insns / c_add.h
1 require_extension('C');
2 if (insn.rvc_rs2() == 0) {
3 if (insn.rvc_rs1() == 0) { // c.ebreak
4 throw trap_breakpoint();
5 } else { // c.jalr
6 reg_t tmp = npc;
7 set_pc(RVC_RS1 & ~reg_t(1));
8 WRITE_REG(X_RA, tmp);
9 }
10 } else {
11 WRITE_RD(sext_xlen(RVC_RS1 + RVC_RS2));
12 }