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[riscv-isa-sim.git] / riscv / insns / c_lui.h
1 require_extension('C');
2 if (insn.rvc_rd() == 2) { // c.addi16sp
3 require(insn.rvc_addi16sp_imm() != 0);
4 WRITE_REG(X_SP, sext_xlen(RVC_SP + insn.rvc_addi16sp_imm()));
5 } else {
6 require(insn.rvc_imm() != 0);
7 WRITE_RD(insn.rvc_imm() << 12);
8 }