Move towards RVC v1.8
[riscv-isa-sim.git] / riscv / insns / c_lui.h
1 require_extension('C');
2 if (insn.rvc_rd() == 0) { // c.addi16sp
3 WRITE_REG(X_SP, sext_xlen(RVC_SP + insn.rvc_addi16sp_imm()));
4 } else {
5 WRITE_RD(insn.rvc_imm() << 12);
6 }