projects / riscv-isa-sim.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
Update README
[riscv-isa-sim.git] / riscv / insns / c_lwsp.h
1 require_extension('C');
2 require(insn.rvc_rd() != 0);
3 WRITE_RD(MMU.load_int32(RVC_SP + insn.rvc_lwsp_imm()));
Simple-V augmented version of spike