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HEAD
Add rest of RV32C instructions
[riscv-isa-sim.git]
/
riscv
/
insns
/
c_sdsp.h
1
require_extension
(
'C'
);
2
if
(
xlen
==
32
) {
3
if
(
sreg_t
(
RVC_RS1S
) <
0
)
// c.bltz
4
set_pc
(
pc
+
insn
.
rvc_b_imm
());
5
}
else
{
6
MMU
.
store_uint64
(
RVC_SP
+
insn
.
rvc_sdsp_imm
(),
RVC_RS2
);
7
}