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HEAD
[sim] changed divide-by-0 semantics
[riscv-isa-sim.git]
/
riscv
/
insns
/
divw.h
1
require_xpr64
;
2
if
(
RS2
==
0
)
3
RD
=
UINT64_MAX
;
4
// INT64_MIN/-1 corner case shouldn't occur in correct code, since
5
// INT64_MIN is not a proper 32-bit signed value
6
else if
(
sreg_t
(
RS1
) ==
INT64_MIN
&&
sreg_t
(
RS2
) == -
1
)
7
RD
=
RS1
;
8
else
9
RD
=
sext32
(
sreg_t
(
RS1
) /
sreg_t
(
RS2
));