riscv/insns/dmtc0.h

   1 require_supervisor;
   2 require64;
   3
   4 switch(insn.rtype.rs)
   5 {
   6   case 0:
   7     set_sr(RT);
   8     break;
   9   case 1:
  10     epc = RT;
  11     break;
  12   case 3:
  13     ebase = RT & ~0xFFF;
  14     break;
  15
  16   case 16:
  17     sim->set_tohost(RT);
  18     break;
  19 }