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[sim,xcc] Changed instruction format to RISC-V
[riscv-isa-sim.git]
/
riscv
/
insns
/
dmulh.h
1
require64
;
2
int64_t
rb
=
RA
;
3
int64_t
ra
=
RB
;
4
RC
= (
int128_t
(
rb
) *
int128_t
(
ra
)) >>
64
;